Arrangement Comprising an Integrated Circuit

• US 20080219441A1
• Filed: 03/10/2005
• Published: 09/11/2008
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: Continental Automotive GmbH (Continental AG)
• Inventors: Lindinger, Andreas, Rombach, Gerhard, Lange, Roland, Kiemes, Jochen, Asperger, Karl
• Granted Patent: US 8,577,031 B2
• Time in Patent Office: Days
• US Class Current: 380/46
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2221/2101 Auditing as a secondary aspect

Abstract

An integrated circuit (1) is provided with function modules (2) which comprise a central processing unit (4) for treating data and executing a program and a cache memory (5). Until now, it was complicated and costly to ensure the manipulation security of the modules. The function modules (2) comprise an encoding unit (6) for data encoding and decoding.

Claims

1. An integrated circuit comprising function modules, wherein the function modules comprise a central processing unit designed to process data and to execute programs, and a cache memory, wherein the function modules comprise an encryption unit designed to encrypt and decrypt data and the function modules comprise a security sensor system by means of which at least one operating parameter of the integrated circuit is monitored, wherein, as operating parameters, the state of a protective layer on the integrated circuit is monitored.

2. The integrated circuit as according to claim 1, wherein the function modules comprise a random-number generator.

3. The integrated circuit according to claim 1, wherein function modules comprise a first memory in which cryptological keys are stored.

4. The integrated circuit according to claim 3, wherein cryptological keys which are stored in the first memory are generated by means of the random-number generator.

5. The integrated circuit according to claim 1, wherein function modules comprise a real-time clock.

6. The integrated circuit according to claim 1, wherein operating parameters to be monitored additionally is the clock frequency of the real-time clock and/or an operating temperature at a point in the integrated circuit and/or an operating voltage of the integrated circuit.

7. The integrated circuit according to claim 1, wherein at least one limit value is predetermined for the operating parameter to be monitored, the operating parameter is measured and compared with the limit value and when the result exceeds or drops below the limit value, the content of the first memory is deleted.

8. The integrated circuit according to claim 1, wherein it is arranged in a package and has terminal contacts brought out of the package.

9. The integrated circuit according to claim 1, wherein individual function modules have an essentially planar extent and are arranged adjacently to one another in the area of the normal to the surface.

10. The integrated circuit according to claim 1, wherein the function modules comprise an integrated voltage regulator which regulates an operating voltage.

11. The integrated circuit according to claim 1, wherein it is constructed as semiconductor chip.

12. The integrated circuit according to claim 11, wherein semiconductor structures of the individual function modules are intermeshed in the manner of a puzzle in order to avoid individual function modules from being recognizable.

13. The integrated circuit according to claim 11, wherein an active protective layer which consists of at least one elongated electrical line which extends along the surface of the die, particularly in mutually parallel tracks section by section, is applied directly to the die of the semiconductor chip.

14. An arrangement comprising an integrated circuit as claimed claim 1, wherein the integrated circuit is connected by means of a data bus to a second memory in which data are stored encrypted, wherein the second memory has memory cells which in each case have a memory address and each memory cell can be addressed directly in reading or writing manner.

15. The arrangement comprising an integrated circuit as claimed claim 14, wherein the second memory is volatile and is connected to a battery so that the voltage supply is maintained when another power supply is lacking.

16. The arrangement comprising an integrated circuit as claimed claim 1, wherein the integrated circuit is connected by means of a data bus to a non-volatile third memory in which data or program code are stored encrypted.

17. The arrangement comprising an integrated circuit according to claim 1, wherein the security sensor system is connected to a battery so that the voltage supply is maintained if another power supply is lacking.

18. The arrangement comprising an integrated circuit according to claim 1, wherein the security sensor system is connected to an auxiliary power source, integrated in the package, which provides the power for deleting the first memory.

19. The arrangement comprising an integrated circuit as claimed claim 16, wherein the third memory is a Flash memory or ROM.

20. An integrated circuit comprising function modules, wherein the function modules comprise a central processing unit designed to process data and to execute programs, and a cache memory, wherein the function modules comprise an encryption unit designed to encrypt and decrypt data and the function modules comprise a security sensor system by means of which at least one operating parameter of the integrated circuit is monitored, wherein, as operating parameters, the state of a protective layer on the integrated circuit is monitored, wherein the function modules comprise a random-number generator and a first memory in which cryptological keys are stored, and wherein cryptological keys which are stored in the first memory are generated by means of the random-number generator.