Efficient On-Chip Accelerator Interfaces to Reduce Software Overhead
First Claim
1. A processor comprising:
- execution circuitry configured to execute a store instruction having a data operand, wherein the execution circuitry is configured to generate a virtual address as part of executing the store instruction; and
a translation lookaside buffer (TLB) coupled to receive the virtual address and configured to translate the virtual address to a first physical address, and wherein the TLB is further coupled to receive the data operand and to translate the data operand to a second physical address.
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Accused Products
Abstract
In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.
60 Citations
21 Claims
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1. A processor comprising:
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execution circuitry configured to execute a store instruction having a data operand, wherein the execution circuitry is configured to generate a virtual address as part of executing the store instruction; and a translation lookaside buffer (TLB) coupled to receive the virtual address and configured to translate the virtual address to a first physical address, and wherein the TLB is further coupled to receive the data operand and to translate the data operand to a second physical address. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A hardware accelerator coupled to receive an indication of a translation lookaside buffer (TLB) invalidation from a processor to which the hardware accelerator is couplable, the hardware accelerator comprising:
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a physical address buffer configured to store one or more physical addresses corresponding to memory locations being accessed by the hardware accelerator; and accelerator execution circuitry coupled to the physical address buffer and configured to perform one or more tasks assigned to the hardware accelerator, wherein the accelerator execution circuitry is configured to transmit an acknowledgement in response to the TLB invalidation indication, responsive to invalidating physical addresses in the physical address buffer that are affected by the TLB invalidation. - View Dependent Claims (9, 10, 11)
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12. A method comprising:
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executing a store instruction having a data operand, wherein the executing comprises generating a virtual address; translating the virtual address to a first physical address; and selectively translating the data operand to a second physical address. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification