Checkpointing user design states in a configurable IC

• US 20080222465A1
• Filed: 03/13/2006
• Published: 09/11/2008
• Est. Priority Date: 07/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Hutchings, Brad, Schmit, Herman, Kronmiller, Tom, Redgrave, Jason
• Granted Patent: US 7,512,850 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC.

Claims

1. A method of debugging a configurable integrated circuit (IC), the method comprising:

a) iteratively starting and stopping the user-design operation of the IC;

b) at each particular stoppage, retrieving a plurality of user-design state values associated with the user-design state of the IC at the particular stoppage without retrieving configuration data;

c) storing the retrieved state values.

2. The method of claim 1 further comprising:

a) encountering an error in the operation of the IC;

b) reloading in the IC the stored user-design state values associated with a stoppage prior to encountering the error;

c) after reloading the user-design state values, re-starting the operation of the IC and monitoring the operation of the IC to identify a source for the error.

3. The method of claim 1, wherein the IC has a plurality of user-design state circuits that store the user-design state of the IC and a debug network communicatively coupled to the user-design state circuits, wherein storing the user-design state values comprises directing the state circuits to output their user-design state values onto the debug network.

4. The method of claim 3, wherein storing the plurality of user-design state values comprises outputting from the IC the user-design state values that are outputted onto the debug network and storing the user-design state values outputted from the IC in a storage outside of the IC.

5. The method of claim 4 further comprising:

a) encountering an error in the operation of the IC;

b) from the storage outside of the IC, reloading in the IC the stored user-design state values associated with a stoppage prior to encountering the error;

c) after reloading the user-design state values, re-starting the operation of the IC and monitoring the operation of the IC to identify the error.

6. The method of claim 3, wherein the state circuits are user design state (UDS) circuits, wherein retrieving the user-design state values further comprises using the debug network to retrieve the user-design state value stored in each UDS circuit at each particular stoppage of the IC.

7. The method of claim 1, wherein iteratively stopping the operation of the IC comprises stopping the operation of the IC at particular intervals.

8. The method of claim 1, wherein iteratively stopping the operation of the IC comprises stopping the operation of the IC after a particular number of operational cycles.

9. The method of claim 1, wherein storing the retrieved state values comprises storing the state values within the IC.

10. A configurable integrated circuit (IC) comprising:

a) a plurality of user design state (UDS) circuits that store state values;

b) a debug network communicatively coupled to the UDS circuits, said debug network for retrieving the user-design state values of a plurality of the UDS circuits at various stoppages of the operation of the IC without retrieving configuration data, wherein the retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC.

11. The configurable IC of claim 10, wherein during debugging, when an error in the operation of the IC is detected, the debug network is further for reloading in the IC the stored user-design state values associated with a stoppage prior to encountering the error.

12. The configurable IC of claim 10, wherein the debug network retrieves user-design state values of the plurality of UDS circuits by carrying the address of said UDS circuits and carrying instructions that direct the addressed UDS circuits to output the user-design state values they store.

13. The configurable IC of claim 12, wherein the debug network outputs from the IC the user-design state values that are outputted onto the debug network so that the user-design state values are stored in a storage outside of the IC.

14. The configurable IC of claim 10, wherein the operation of the IC is iteratively stopped at particular intervals.

15. The configurable IC of claim 10, wherein the operation of the IC is iteratively stopped after a particular number of operational cycles.

16. A configurable integrated circuit (IC) comprising:

a plurality of user design state (UDS) circuits that store user-design state values;

a debug network communicatively coupled to the UDS circuits, said debug network for performing a debugging operation that stops the user-design operations of the IC at different times during the user-design operations of the IC and retrieves different user-design state values of a plurality of the UDS circuits from only a portion of the IC.

17. The configurable IC of claim 16, wherein during debugging operations, when an error in the operation of the IC is detected, the debug network is further for reloading in the IC the stored user-design state values associated with a stoppage prior to encountering the error.

18. The configurable IC of claim 16, wherein the debug network retrieves user-design state values of the plurality of UDS circuits by carrying the address of said UDS circuits and carrying instructions that direct the addressed UDS circuits to output the user-design state values they store.

19. The configurable IC of claim 18, wherein the debug network outputs from the IC the user-design state values that are outputted onto the debug network so that the user-design state values are stored in a storage outside of the IC.