Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure

• US 20080222584A1
• Filed: 04/21/2008
• Published: 09/11/2008
• Est. Priority Date: 07/24/2006
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: McMahon, Robert, Habib, Nazmul, Perry, Troy
• Application Number:
  US12/106,373
• Publication Number:
  US 20080222584A1
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

A method in a computer-aided design system for generating a functional design model of a test structure. The test structure is used for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip generated from the functional design model is tested individually without excessive test time requirements, additional silicon, or special test equipment. The method includes a functional representation of a device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of functional representations of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design.

Claims

1. A method in a computer-aided design system for generating a functional design model of a test structure, said method comprising:

identifying at least one functional representation of a device under test (DUT) which matches at least one functional representation of a device in an integrated circuit (IC) design;

generating a functional representation of a first test structure comprising a functional representation of a control structure coupled to the at least one DUT; and

modifying the IC design to include the functional representation of the first test structure.

2. The method of claim 1 further comprising:

generating a list of a plurality of functional representations of DUTs which match at least one of a plurality of functional representations of devices in the integrated circuit design.

3. The method of claim 2 further comprising:

generating a prioritized list from the list of the plurality of functional representations of DUTs using at least one prioritization algorithm and at least one of a plurality of customer directives, a plurality of historical data, or a plurality of internal rules.

4. The method of claim 2 further comprising

storing in a database at least one of the plurality of functional representations of DUTs which is in the list but which is not in the functional representation of the first test structure.

5. The method of claim 3, further comprising:

using at least one of a plurality of placement algorithms to place the at least one functional representation of the DUT from the prioritized list into the design.

6. The method of claim 1 further comprising:

determining whether area is available in the functional representation of the integrated circuit for the functional representation of first test structure.

7. The method of claim 1 further comprising:

determining whether a functional representation of an element is available in the functional representation of integrated circuit for coupling to the functional representation of the first test structure.

8. The method of claim 1 further comprising:

assigning the functional representation of the control structure to the functional representation of the element in the IC design.

9. The method of claim 8 further comprising:

storing the assignment in an assignment list.

10. The method of claim 8 further comprising:

compiling the IC design; and

performing a plurality of design checking algorithms.