Semiconductor Nanowire and Semiconductor Device Including the Nanowire

• US 20080224122A1
• Filed: 12/21/2005
• Published: 09/18/2008
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: JOLED Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kawashima, Takahiro, Saitoh, Tohru
• Granted Patent: US 7,629,629 B2
• Time in Patent Office: Days
• US Class Current: 257/14
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A nanowire (100) according to the present invention includes a plurality of contact regions (10a, 10b) and at least one channel region (12), which is connected to the contact regions (10a, 10b). The channel region (12) is made of a first semiconductor material and the surface of the channel region (12) is covered with an insulating layer that has been formed selectively on the channel region (12). The contact regions (10a, 10b) are made of a second semiconductor material, which is different from the first semiconductor material for the channel region (12), and at least the surface of the contact regions (10a, 10b) includes a conductive portion.

Claims

1. A nanowire comprising

a plurality of contact regions, and

at least one channel region, which is connected to the contact regions,

wherein the channel region is made of a first semiconductor material and the surface of the channel region is covered with an insulating layer that has been formed selectively on the channel region, and

wherein the contact regions are made of a second semiconductor material, which is different from the first semiconductor material for the channel region, and at least the surface of the contact regions includes a conductive portion.

2. The nanowire of claim 1, wherein the first semiconductor material is Si_xGe_1-x (where 0<

x≦

1) and the second semiconductor material is Si_yGe_1-y (where 0≦

y<

1 and x≠

y).

3. The nanowire of claim 1, wherein the insulating layer is made of an oxide of the first semiconductor material.

4. The nanowire of claim 3, wherein the insulating layer is formed by thermally oxidizing the surface of the channel region.

5. The nanowire of claim 1, wherein the insulating layer covers the surface of the channel region but does not cover the surface of the contact regions.

6. The nanowire of claim 1, wherein the channel region has a length of 1,000 nm or less as measured along the axis of the nanowire.

7. The nanowire of claim 1, wherein the conductive portion of the contact regions is made of the second semiconductor material that has been doped with a dopant and that has a higher conductivity than the channel region.

8. The nanowire of claim 1, wherein the conductive portion of the contact regions is made of an alloy in which a constituent element of the second semiconductor material and a metal element are bonded together.

9. The nanowire of claim 8, wherein the contact regions include a core portion, which is made of a semiconductor material including an element that is bonded to the metal element in the conductive portion.

10. The nanowire of claim 9, wherein the alloy is either a metal compound of silicon or a metal compound of germanium.

11. The nanowire of claim 1, wherein the number of the contact regions is N, which is an integer equal to or greater than three, and the number of the channel region is M, which is N−

1.

12. The nanowire of claim 11, wherein the contact regions and the channel regions are alternately arranged at a predetermined pitch along the axis of the nanowire.

13. The nanowire of claim 11, wherein the nanowire is arranged between two electrodes, each of which is electrically in contact with at least a portion of the contact regions of the nanowire, and

wherein if the length of each said channel region is L_ch, the distance between the two electrodes is L_SD, the length of the contact regions is L_cont, the length of one of the two electrodes in a channel length direction is L_S, and the length of the other electrode in the channel length direction is L_D, the following inequalities:

L_S>

L_ch 

 

(1)

L_D>

L_ch 

 

(2)

L_SD>

L_cont 

 

(3)

are satisfied.

24. A method for fabricating an electronic device, the method comprising the steps of:

preparing a solvent in which the nanowires of claim 1 are dispersed;

applying the solvent onto a substrate; and

bringing the contact regions of at least one of the nanowires in the solvent into contact with electrodes.

25. The method of claim 24, wherein the step of applying the solvent onto the substrate includes the step of aligning the nanowires, dispersed in the solvent, in a particular direction.

14. A method of making a nanowire, the method comprising the steps of:

(A) providing a nanowire member that includes a portion made of a first semiconductor material and a portion made of a second semiconductor material, which is different from the first semiconductor material; and

(B) selectively forming an insulating layer on the surface of the portion of the nanowire member that is made of the first semiconductor material and making at least the surface of the portion of the nanowire that is made of the second semiconductor material function as a conductive portion.

15. The method of claim 14, further comprising the step (C) of alloying the surface of the portion of the nanowire member that is made of the second semiconductor material with a metal element by causing a chemical reaction between the surface and the metal element.

16. The method of claim 14, wherein the step (A) includes the steps of:

(a1) growing the first semiconductor material under a first crystal-growing condition; and

(a2) growing the second semiconductor material under a second crystal-growing condition, which is different from the first crystal-growing condition.

17. The method of claim 14, wherein the step (B) includes the steps of:

(b1) oxidizing the surface of the first and second semiconductor materials of the nanowire member, thereby forming an oxide film on the surface; and

(b2) selectively removing a portion of the oxide film from the surface of the second semiconductor material, thereby leaving the other portion of the oxide film on the surface of the first semiconductor material.

18. The method of claim 17, wherein the step (C) includes the steps of:

(c1) forming a metal layer over the first and second semiconductor materials of the nanowire member;

(c2) alloying the metal layer with the surface of the second semiconductor material where the metal layer and the surface contact with each other; and

(c3) selectively removing a non-alloyed portion of the metal layer.

19. An electronic element comprising

at least one nanowire, and

a plurality of electrodes, which are electrically connected to the nanowire,

wherein each said nanowire includes:

a plurality of contact regions, including two contact regions that contact with associated ones of the electrodes, and at least one channel region, which is connected to the contact regions, and

wherein the channel region is made of a first semiconductor material and is covered with an insulating layer that has been formed selectively on the channel region, and

wherein the contact regions are made of a second semiconductor material, which is different from the first semiconductor material, and at least the surface of the contact regions includes a conductive portion.

20. The electronic element of claim 19, further comprising a gate electrode, which is insulated from the channel region and which applies an electric field to the channel region.

21. The electronic element of claim 19, wherein the channel region has a length of 1,000 nm or less as measured along the axis of the nanowire.

22. An electronic device comprising:

a plurality of electronic elements of claim 20;

a line for connecting the electrodes together; and

a substrate for supporting the electronic elements and the line thereon.

23. The electronic device of claim 22, wherein the nanowires included in the electronic elements are aligned in a particular direction on the substrate.