Fabrication Transistors

• US 20080224173A1
• Filed: 09/01/2006
• Published: 09/18/2008
• Est. Priority Date: 10/19/2005
• Status: Active Grant

• Current Assignee: Tinggi Technologies Pte., Ltd.
• Original Assignee: Tinggi Technologies Pte., Ltd.
• Inventors: Lin, Shi Ming, Yuan, Shu, Kang, Xue Jun
• Granted Patent: US 8,067,269 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

A method for fabricating transistors such as high electron mobility transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising: (a) forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; (b) forming at least one drain contact on the first surface; (c) forming at least one gate contact on the first surface; (d) forming at least one insulating layer over and between the gate contacts, source contacts and the drain contacts; (e) forming a conductive layer over at least a part of the at least one insulating layer for connecting the source contacts; and (f) forming at least one heat sink layer over the conductive layer.

Claims

1. A method for fabricating transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising:

forming a plurality of source contacts on a first surface of the plurality of epitaxial layers;

forming at least one drain contact on the first surface;

forming at least one gate contact on the first surface;

forming at least one layer of insulating material over and between the gate contact, source contacts and the drain contact for insulating the gate contact, source contacts and the drain contact;

forming a conductive layer over and through at least a part of the at least one insulating layer for connecting the source contacts;

forming at least one seed layer on the conductive layer; and

forming at least one heat sink layer over the seed layer.

2. The method as claimed in claim 1, wherein the transistors are high electron mobility transistors, the plurality of epitaxial layers comprising a layer of gallium nitride, a layer of aluminium gallium nitride, a layer of n+ aluminium gallium nitride and a final layer of gallium nitride;

the first surface being on the final layer of gallium nitride;

the at least one layer of insulating material being electrically insulating but heat conductive;

the conductive layer connecting the plurality of source contacts through vias in the at least one insulating layer.

3. The method as claimed in claim 1, wherein the at least one heat sink layer is a relatively thick layer of conductive metal formed over the conductive layer, the relatively thick layer of conductive metal being for at least one selected from the group consisting of:

a structural support, a heat sink, a heat dissipater, and as a connector.

4. The method as claimed in claim 1, wherein the seed layer comprises a plurality of seed layers, wherein a first of the plurality of seed layers is applied to the conductive layer, the first seed layer being of a material that has a first co-efficient of thermal expansion;

and a second seed layer is formed on the first seed layer, the second seed layer being of a material that has a second co-efficient of thermal expansion, the second co-efficient of thermal expansion being greater than the first co-efficient of thermal expansion;

one of the first seed layer and the second seed layer being a diffusion barrier for providing a barrier to diffusion of a layer applied to it from diffusing into the epitaxial layers.

7. The method as claimed in claim 1, wherein a source connection is formed by creating then filling at least one via through the common substrate and the plurality of epitaxial layers to the conductive layer.

8. The method as claimed in claim 1, wherein a drain connection is formed by creating then filing at least one via through the common substrate and the plurality of epitaxial layers to the at least one drain contact, a gate connection is formed by creating then filling at least one via through the common substrate and the plurality of epitaxial layers to the at least one gate contact, and a source connection is formed by forming then filling at least one via through the plurality of epitaxial layers to the conductive layer.

10. The method as claimed in claim 1, further comprising removing the substrate after the at least one heat sink layer is formed;

and forming a further layer of electrically insulating and heat conductive material in place of the substrate.

12. The method as claimed in claim 10, wherein a source connection is formed by forming then filling at least one via through the plurality of epitaxial layers to the conductive layer, a drain connection is formed by creating then filing at least one via through the plurality of epitaxial layers to the at least one drain contact, and a gate connection is formed by creating then filling at least one via through the plurality of epitaxial layers to the at least one gate contact.

14. The method as claimed in claim 1, wherein patterned plating is performed before the at least one heat sink layer is formed.

5-6. -6. (canceled)

9. (canceled)

11. (canceled)

13. (canceled)

15. Apparatus comprising transistors, each comprising:

(a) a plurality of epitaxial layers having a first surface;

(b) a plurality of source contacts, at least one drain contact and at least one gate contact, all on the first surface;

(c) at least one insulating layer over and between the source contacts, the at least one drain contact and the at least one gate contact for insulating the gate contact, source contact and the drain contact;

(d) a conductive layer over and through at least a part of the at least one insulating layer for connecting the source contacts;

(e) at least one heat sink layer over the conductive layer; and

(f) at least one seed layer between the conductive layer and the at least one heat sink layer.

16. The apparatus as claimed in claim 15, wherein the at least one heat sink layer is over the conductive layer and the at least one insulating layer not covered by the conductive layer, the at least one insulating layer being electrically insulating and heat conductive.

18. The apparatus as claimed in claim 15, wherein the plurality of epitaxial layers comprises a layer of gallium nitride, a layer of aluminum gallium nitride, a layer of n+ aluminum gallium nitride and a final layer of gallium nitride, the first surface being on the final layer of gallium nitride.

19. The apparatus as claimed in claim 15, wherein the conductive layer connects the plurality of source contacts through vias in the at least one insulating layer.

20. The apparatus as claimed in claim 16, wherein the at least one heat sink layer is a relatively thick layer of conductive metal over the conductive layer, the relatively thick layer being for at least one selected from the group consisting of:

a structural support, a heat sink, a heat dissipater, and a connector.

21. The apparatus as claimed in claim 15, wherein the seed layer comprises a plurality of seed layers, wherein a first of the plurality of seed layers is on the conductive layer, the first seed layer being of a material that has a first co-efficient of thermal expansion;

and a second seed layer is on the first seed layer, the second seed layer being of a material that has a second co-efficient of thermal expansion, the second co-efficient of thermal expansion being greater than the first co-efficient of thermal expansion, one of the first seed layer and the second seed layer being a diffusion barrier for providing a barrier to diffusion of a layer applied to it from diffusing into the epitaxial layers.

24. The apparatus as claimed in claim 15, further comprising a source connection through the common substrate and the plurality of epitaxial layers to the conductive layer, a drain connection through the common substrate and the plurality of epitaxial layers to the at least one drain contact, and a gate connection through the common substrate and the plurality of epitaxial layers to the at least one gate contact.

27. The apparatus as claimed in claim 20, wherein the substrate is removed after the relatively thick layer of conductive metal is formed.

28. The apparatus as claimed in claim 27, further comprising a layer of electrically insulating and heat conductive material in place of the substrate.

29. The apparatus as claimed in claim 27, further comprising a source connection through the plurality of epitaxial layers to the conductive layer, a drain connection through the plurality of epitaxial layers to the at least one source contact and a gate connection through the plurality of epitaxial layers to the at least one gate contact.

31. The apparatus as claimed in claim 16, wherein the at least one heat sink layer comprises the relatively thick layer of conductive metal, the at least one seed layer, the conductive layer and the at least one insulating layer.

32. The apparatus as claimed in claim 15, wherein the transistors are high electron mobility transistors.

17. (canceled)

22-23. -23. (canceled)

25-26. -26. (canceled)

30. (canceled)

33-35. -35. (canceled)