RESISTIVE MEMORY AND METHOD

• US 20080224178A1
• Filed: 03/16/2007
• Published: 09/18/2008
• Est. Priority Date: 03/16/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies Batam PT (Infineon Technologies AG), Qimonda Aggustav
• Inventors: Kund, Michael, Pacha, Christian, Schonauer, Tim
• Granted Patent: US 8,063,448 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/883 Oxides or nitrides

Abstract

A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Claims

1. A memory device comprising:

a multi gate field effect transistor having a fin with a contact area; and

a programmable memory element abutting the fin contact area.

2. The memory device of claim 1 wherein the programmable memory element comprises a resistive memory.

3. The memory device of claim 2 comprises one of a resistive phase change random access memory (PC-RAM), a conductive bridge random access memory (CB-RAM), a resistive random access memory (R-RAM), a nano-random access memory, or an oxide-resistive memory (OX-RAM).

4. The memory device of claim 1 wherein the contact area is smaller than an area of a programmable volume portion of the resistive memory that it abuts.

5. The memory device of claim 1 wherein the fin is longitudinally tapered toward the contact area.

6. The memory device of claim 1 wherein the fin is tapered to reduce one of its height and width in the contact area.

7. A memory device comprising:

a multi gate field effect transistor having a first fin with a cross sectional contact area at a drain or source of the multi gate field effect transistor; and

a resistive memory element abutting the fin contact area.

8. The memory device of claim 7 wherein the fin and resistive memory element are arranged in a lateral manner supported by a substrate.

9. The memory device of claim 7 wherein the multi gate field effect transistor is electrically isolated from the substrate.

10. The memory device of claim 7 wherein the contact area of the fin is reduced.

11. The memory device of claim 7 wherein the contact area is formed in a shape that modifies electrical characteristics of the resistive memory element.

12. A memory device comprising:

a multi gate field effect transistor having a fin with source and drain regions, and with a fin contact area adjacent the drain region;

a first contact block formed adjacent the source region of the fin;

a programmable memory element abutting the fin contact area; and

a second contact block coupled to the programmable memory element.

13. The memory device of claim 12 and further comprising a gate coupled to the fin between the source and drain region and further coupled to a word line.

14. The memory device of claim 13 wherein the first contact block is coupled to ground and wherein the second contact block is coupled to the bitline.

15. The memory device of claim 14 and further comprising multiple memory devices coupled to word and bit lines to form an addressable array of memory devices.

16. A memory device comprising:

a multi gate field effect transistor having multiple first fins controlled by a gate line that couples multiple planes of the first fins;

at least one second fin coupled at one end to the multiple first fins and having a contact area adjacent the other end; and

a resistive memory element abutting each fin contact area.

17. The memory device of claim 16 wherein there are two first fins.

18. The memory device of claim 16 wherein the contact area is smaller than an area of the resistive memory that it abuts.

19. The memory device of claim 16 wherein the fin is tapered toward the contact area.

20. The memory device of claim 16 wherein the fin is tapered to reduce one of its width and height adjacent the contact area.

21. A method of interacting with a resistive memory, the method comprising:

controlling current through a fin or multiple connected fins of a multi gate field effect transistor; and

interacting with a programmable volume portion of a resistive memory element abutting an end of the fin.

22. The method of claim 21 wherein interacting comprises applying a write current.

23. The method of claim 21 wherein interacting comprises applying a reset current.

24. The method of claim 21 wherein interacting comprises applying a read current.