NON-VOLATILE MEMORY

• US 20080224202A1
• Filed: 05/29/2008
• Published: 09/18/2008
• Est. Priority Date: 09/28/2005
• Status: Abandoned Application

• Current Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: Young, Rex, Wang, Pin-Yao
• Application Number:
  US12/129,652
• Publication Number:
  US 20080224202A1
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates.

Claims

1. A non-volatile memory, comprising:

a substrate;

a plurality of isolation layers, disposed in the substrate;

a plurality of active layers, disposed in the substrate and between the isolation layers, wherein the top surface of the active layer is higher than that of the isolation layer, and the active layers and the isolation layers are arranged in parallel to each other and extend in a first direction;

a plurality of control gates, disposed in the substrate, wherein the control gates are arranged in parallel and extend in a second direction which crosses the first direction;

a plurality of floating gates, disposed between the active layers and the control gates; and

a plurality of doped regions, disposed in the active layers between the control gates.

2. The non-volatile memory of claim 1, further comprising a plurality of tunneling dielectric layers disposed between the floating gates and the active layers, wherein the tunneling dielectric layers present in a converse U shape and cover the active layers protruding out of the surface of the isolation layers.

3. The non-volatile memory of claim 1, further comprising a plurality of inter-gate dielectric layers, presenting in a converse U shape, disposed between the control gates and the floating gates.

4. The non-volatile memory of claim 3, wherein the material of the inter-gate dielectric layers comprises silicon oxide-silicon nitride-silicon oxide.

5. The non-volatile memory of claim 1, wherein the floating gates are disposed on the two sidewalls of the active layers.

6. The non-volatile memory of claim 1, wherein the substrate comprises a silicon on insulator (SOI) substrate.

7. The non-volatile memory of claim 1, wherein the non-volatile memory is an NAND type flash memory.