ATOMIC LAYER DEPOSITION OF Zrx Hfy Sn1-x-y O2 FILMS AS HIGH k GATE DIELECTRICS

• US 20080224240A1
• Filed: 05/23/2008
• Published: 09/18/2008
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,875,912 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: C23C 16/40 Oxides
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45531 specially adapted for making ternary or higher compositions
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO₂), hafnium oxide (HfO₂) and tin oxide (SnO₂) acting as a single dielectric layer with a formula of Zr_x Hf_y Sn_1-x-y O₂, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Claims

1. An electronic device comprising:

an amorphous dielectric layer containing at least one atomic layer deposited dielectric layer including zirconium oxide, hafnium oxide and tin oxide layers in an integrated circuit; and

a conductive layer contacting the dielectric layer.

2. The electronic device of claim 1, wherein the electronic device includes a transistor in the integrated circuit, the transistor having the dielectric layer as a gate insulator and the conductive layer as a gate in the transistor.

3. The electronic device of claim 1, wherein the electronic device includes a CMOS transistor in the integrated circuit, the CMOS transistor having the dielectric layer as a gate insulator and the conductive layer as a gate.

4. The electronic device of claim 1, wherein the electronic device includes a capacitor having the dielectric layer as a dielectric material between two electrodes in the capacitor, and the conductive layer as at least one of the two electrodes.

5. The electronic device of claim 1, wherein the dielectric layer has a general formula of Zr_XHf_YSn_ZO₂.

6. The electronic device of claim 5, wherein X has a range of from 0.70 to 0.85, Y has a range of from 0.05 to 0.25, and Z=1−

X−

Y.

7. The electronic device of claim 6, wherein X is 0.81, Y is 0.12, and Z is 0.07.

8. A system comprising:

a controller;

an electronic device coupled to the controller, wherein the electronic device includes;

a dielectric layer comprising an atomic layer deposited dielectric layer of zirconium oxide, hafnium oxide and tin oxide in an integrated circuit; and

a conductive layer contacting the dielectric layer.

9. The system of claim 8, wherein the electronic device includes a memory.

10. The system of claim 8, wherein the dielectric layer has a general formula of Zr_XHf_YSn_ZO₂.

11. The system of claim 10, wherein X has a range of from 0.70 to 0.85, Y has a range of from 0.05 to 0.25, and Z=1−

X−

Y.

12. The system of claim 10, wherein X is 0.81, Y is 0.12, and Z is 0.07.

13. An electronic device comprising:

a dielectric layer containing at least one layer of zirconium oxide having a first thickness, at least one layer of hafnium oxide having a second thickness, and at least one layer of tin oxide having a third thickness;

the dielectric layer having a dielectric constant greater than 17.0, a thickness of less than 2.0 nm, and a leakage current of less than 10<sup>−

8</sup> Amps/cm²; and

a conductive layer contacting the dielectric layer.

14. The electronic device of claim 13, wherein the electronic device includes at least one transistor including the dielectric layer as a gate insulator and the conductive layer as a gate electrode.

15. The electronic device of claim 14, wherein the electronic device includes a CMOS logic gate including the dielectric layer as a gate insulator and the conductive layer as a gate electrode.

16. The electronic device of claim 13, further including a capacitor including the dielectric layer disposed between two conductive materials to electrically separate them.

17. The device of claim 13, wherein the dielectric layer includes an amorphous structure up to a temperature of 1000 deg C.

18. The device of claim 13, wherein the dielectric layer thickness is about 2.0 nm with a variation of less than 0.20 nm on a horizontal surface.

19. The device of claim 13, wherein the dielectric layer includes a horizontal surface smoothness variation of one percent root mean square of the dielectric layer average thickness.

20. The device of claim 13, wherein the dielectric layer includes a tin oxide percentage of from 5 to 15.

21. The device of claim 13, wherein the dielectric layer is disposed upon a diffusion barrier layer.

22. The device of claim 13, wherein the dielectric layer includes a bandgap value of greater than 5.6 eV.

23. The device of claim 13, wherein the dielectric layer comprises a first plurality of individual layers of zirconium oxide each layer having a first thickness of about 0.12 nm, a second plurality of individual layers of hafnium oxide each layer having a second thickness of about 0.33 nm, and a third plurality of individual layers of tin oxide each layer having a third thickness of about 0.18 nm.

24. The device of claim 23, wherein the individual layers of the first, second and third pluralities of individual layers are interleaved between each other.

25. A metal oxide semiconductor transistor;

comprising;

a semiconductor substrate of a first doping type and a first concentration level;

at least two diffusion regions in the substrate having a second and opposite doping type, and a second and higher concentration level;

a channel region disposed between and to electrically separate the at least two diffusion regions;

a dielectric layer having a first thickness disposed above the channel region and above at least a portion of the at least two diffusion regions, including at least three different metal oxide materials, having an overall layer dielectric constant of greater than 17.0, and a physical thickness of less than 20 nm; and

a conductive gate electrode material disposed above the dielectric layer and above at least a portion of the at least two diffusion regions.

26. The transistor of claim 25, wherein the at least three different metal oxide materials include a first plurality of individual layers of a first one of the at least three different metal oxide materials, a second plurality of individual layers of a second one of the at least three different metal oxide materials, and a third plurality of individual layers of a third one of the at least three different metal oxide materials.

27. The transistor of claim 26, wherein at least some of the individual layers of the first plurality of individual layers of a first one of the least three different metal oxide materials are in direct contact on a top surface with a different one of the at least three different metal oxide materials, and in direct contact on a bottom surface with a remaining one of the at least three different metal oxide materials.

28. The transistor of claim 25, wherein the dielectric layer has an overall layer composition formula of Zr_XHf_YSn_ZO₂.

29. The transistor of claim 28, wherein X is between 0.70 to 0.85, Y is between 0.05 to 0.25, and Z=1−

X−

Y.

30. The transistor of claim 29, wherein X is about 0.81, Y is about 0.12, and Z is about 0.07.

31. The transistor of claim 28, wherein the at least three different metal oxide material individual layers are interleaved such that a local composition of the dielectric film has a smoothly continuous grading between substantially pure ZrO₂ at a bottom portion of the dielectric film disposed near the channel region, to substantially pure HfO₂ at a top portion of the dielectric film disposed near the conductive gate electrode material.

32. The transistor of claim 25, wherein a diffusion barrier layer is disposed between a bottom portion of the dielectric layer and a top portion of the channel region.