Programmable Vias for Structured ASICs

• US 20080224260A1
• Filed: 03/12/2008
• Published: 09/18/2008
• Est. Priority Date: 03/13/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Schmit, Herman, Park, Jonathan, Levinthal, Adam, Vasishta, Ronnie
• Granted Patent: US 8,339,844 B2
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Claims

1. A semiconductor device comprising:

a number of metal layers having vias formed among and between them;

a further metal layer overlying an uppermost metal layer of the number of metal layers; and

a via layer between the further metal layer and the uppermost metal layer, the via layer comprising one or more programmable vias between one or more segments of the uppermost metal layer and the further metal layer, said one or more programmable vias comprising at least one material having a changeable resistance.

2. The semiconductor device according to claim 1, wherein the at least one material having a changeable resistance comprises a phase change material.

3. The semiconductor device according to claim 1, wherein the at least one material having a changeable resistance is capable of having its resistance changed by exposure to an electric signal.

4. The semiconductor device according to claim 3, further comprising:

a first shift register to address said programmable vias; and

a second shift register to address said programmable vias,

wherein the first and second shift registers are to be programmed with data to specify a set of said programmable vias.

5. The semiconductor device according to claim 4, further comprising:

one or more transistors, each coupled to either the first shift register or the second shift register, to provide electric current across one or more of said set of said programmable vias.

6. The semiconductor device according to claim 1, wherein the at least one material having a changeable resistance is capable of having its resistance changed by exposure to one or more laser beams.

7. The semiconductor device according to claim 1, further comprising:

one or more buffers inserted at one or more points to limit a number of vias in high-resistance states that are connected to a particular metal segment.

8. The semiconductor device according to claim 1, further comprising:

at least one pass transistor or at least one tri-state buffer coupled to a metal segment having high-resistance-state vias coupled to power and to ground.

9. The semiconductor device according to claim 1, wherein said via layer includes at least one non-programmable via.

10. A method of fabricating a semiconductor device, the method comprising:

forming a number of metal layers having vias formed among and between them;

forming a via layer on top of an uppermost one of the number of metal layers, said via layer being formed using at least one material having a changeable resistance; and

forming a further metal layer on top of said via layer, wherein said via layer is adapted to provide at least one programmable via between said uppermost metal layer and said further metal layer.

11. The method according to claim 10, wherein the at least one material having a changeable resistance comprises a phase change material.

12. The method according to claim 10, wherein the at least one material having a changeable resistance is capable of having its resistance changed by exposure to an electric signal.

13. The method according to claim 10, wherein the at least one material having a changeable resistance is capable of having its resistance changed by exposure to one or more laser beams.

14. The method according to claim 10, further comprising:

forming at least a first shift register and a second register coupled to said via layer to enable programming of one or more vias of said via layer.

15. The method according to claim 14, further comprising:

forming one or more transistors, each coupled to either the first shift register or the second shift register and also coupled to a via of said via layer.

16. The method according to claim 10, further comprising:

forming one or more buffers at one or more points, the points located in said uppermost metal layer, said further metal layer, or both, to limit a number of vias in high-resistance states that are connected to a particular metal segment.

17. The method according to claim 10, further comprising:

forming at least one pass transistor or at least one tri-state buffer coupled to a metal segment having high-resistance-state vias coupled to power and to ground.

18. The method according to claim 10, wherein said forming a via layer includes forming at least one non-programmable via in said via layer.

19. A method of using a programmable semiconductor device, the semiconductor device including a number of metal layers having interconnections among and between them, a via layer including at least one programmable via formed from at least one material having a changeable resistance and being formed atop an uppermost one of the number of metal layers, and a further metal layer on top of said programmable via layer, the method comprising:

programming said at least one programmable via of said via layer to selectively form at least one connection between segments of said uppermost metal layer and said further metal layer or to electrically isolate at least one segment of said uppermost metal layer and at least one segment of said further metal layer.

20. The method according to claim 19, wherein the at least one material having a changeable resistance comprises a phase change material.

21. The method according to claim 19, wherein said programming comprises:

exposing at least one programmable via of said via layer to an electric signal to change its resistance.

22. The method according to claim 21, wherein said programming further comprises:

changing a temperature of at least one programmable via of said via layer.

23. The method according to claim 19, wherein said programming comprises:

exposing at least one programmable via of said via layer to a laser beam to change its resistance.

24. The method according to claim 23, wherein said exposing comprises using an offset angle to aim the laser beam.

25. The method according to claim 23, wherein said exposing comprises using multiple focused beams to provide energy to a particular via location.