CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS

• US 20080224273A1
• Filed: 03/07/2008
• Published: 09/18/2008
• Est. Priority Date: 04/20/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Messenger, Brian W., Johnston, Steven H., AMERICA, William G.
• Granted Patent: US 8,106,485 B2
• Time in Patent Office: Days
• US Class Current: 257/622
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

Abstract

A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.

Claims

1. A semiconductor device comprising a plasma etched dual damascene structure with an interlevel dielectric film whereby damage to a surface of the plasma etched dual damascene structure is removed by a method comprising:

depositing a controlled amount of gaseous hydrofluoric acid and ammonia gas onto the surface of the dual damascene structure;

forming volatile reaction products from a chemical reaction between the plasma induced damages and the deposited mixture of ammonia gas and gaseous hydrofluoric acid; and

removing the volatile reaction products.

2. The semiconductor device according to claim 1, wherein the interlevel dielectric film comprises low k material having a dielectric constant of 3.9 or less.

3. The semiconductor device according to claim 1, wherein the damage is removed by trimming a surface between 1 and 25 nm.

4. The semiconductor device of claim 1, wherein the interlevel dielectric film comprises organic siloxanes.

5. The semiconductor device of claim 1, wherein the surface comprises a plasma induced damaged layer formed in a trench sidewall.

6. The semiconductor device of claim 1, wherein the volatile reaction products are removed with a vacuum.

7. The semiconductor device of claim 1, wherein the volatile reaction products are removed with a non-reactive flushing gas.

8. The semiconductor device of claim 1, wherein the volatile reaction products are removed with a vacuum or a non-reactive flushing gas.

9. The semiconductor device of claim 1, further comprising a trench formed in the interlevel dielectric film.

10. The semiconductor device of claim 9, further comprising a barrier layer comprising Si₃N₄ formed on a silicon wafer, wherein the interlevel dielectric film is formed on the barrier layer.

11. The semiconductor device of claim 10, wherein the trench extends through the barrier layer to the silicon wafer.