SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20080224322A1
• Filed: 03/14/2008
• Published: 09/18/2008
• Est. Priority Date: 03/15/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: SHINOGI, Hiroyuki
• Granted Patent: US 8,373,278 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

This invention is directed to offer a semiconductor device having a stacked layer structure and its manufacturing method that bring high yield and reliability. Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. As described above, a process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form.

Claims

1. A semiconductor device comprising:

a base substrate comprising a wiring layer;

a plurality of dice stacked on the base substrate and electrically connected to the wiring layer; and

a protection layer covering the dice and comprising a plurality of resin layers, each resin layer having different hardness from another resin layer.

2. The semiconductor device of claim 1, wherein the wiring layer comprises a through hole electrode formed in the base substrate.

3. The semiconductor device of claim 1, wherein one of the dice comprises a through hole electrode formed in the one of the dice.

4. A semiconductor device comprising:

a base substrate comprising a wiring layer;

a stack of a first die and a second die disposed on the base substrate and electrically connected to the wiring layer, the stack having a side surface, and the second die having a recess portion receding from the side surface;

a third die disposed in the recess portion of the second die; and

a protection layer covering the first, second and third dice.

5. The semiconductor device of claim 4, further comprising a fourth die disposed on the base substrate, wherein the third die comprises a conductive layer electrically connecting the fourth die and the wiring layer.

6. The semiconductor device of claim 4, wherein the third die is disposed in the recess portion so that a side surface of the third die is aligned with the side surface of the stack.

7. The semiconductor device of claim 5, wherein the third die is disposed in the recess portion so that a side surface of the third die is aligned with the side surface of the stack.

8. The semiconductor device of claim 4, further comprising a through hole electrode formed in the first die or second die.

9. The semiconductor device of claim 5, further comprising a through hole electrode formed in the first die or second die.

10. The semiconductor device of claim 4, wherein the first die is disposed between the base substrate and the second die.

11. A method of manufacturing a semiconductor device, comprising:

providing a plurality of dice;

testing the dice to select good dice;

stacking a plurality of the selected good dice on a base substrate having a wafer form;

forming a first resin layer so as to cover the stacked good dice;

forming a second resin layer so as to cover the first resin layer, the second resin layer having hardness different from the first resin layer; and

cutting the base substrate along a predetermined line.

12. A method of manufacturing a semiconductor device, comprising:

providing a plurality of dice;

testing the dice to select good dice;

attaching a first good die and a second good die to the base substrate having a wafer form so as to form a stack, the stack having a side surface, and the second good die having a recess portion receding from the side surface;

placing a third good die in the recess portion of the second die;

forming a protection layer so as to cover the first, second and third good dice; and

cutting the base substrate along a predetermined line.