Chip structure with bumps and testing pads

• US 20080224326A1
• Filed: 05/27/2008
• Published: 09/18/2008
• Est. Priority Date: 12/08/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chien-Kang, Lin, Chu-Fu, Chou, Chiu-Ming, Kuo, Nick
• Granted Patent: US 7,855,461 B2
• Time in Patent Office: Days
• US Class Current: 257/780
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4

Abstract

A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

Claims

1. A chip comprising:

a silicon substrate;

multiple MOS devices in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first circuit layer and a second circuit layer over said first circuit layer, and wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second circuit layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said metallization structure and exposes said first contact point, wherein said passivation layer has a thickness greater than 0.35 micrometers, and wherein said passivation layer comprises a nitride layer;

a first metal layer over said passivation layer and on said first contact point, wherein said first metal layer is connected to said first contact point through said first opening, wherein said first metal layer has a thickness greater than 0.6 micrometers, greater than that of said first circuit layer and greater than that of said second circuit layer, and wherein said first metal layer comprises a first titanium-containing layer and a first copper layer over said first titanium-containing layer;

a first polymer layer over said passivation layer and over said first metal layer, wherein a second opening in said first polymer layer is over a second contact point of said first metal layer and exposes said second contact point, and wherein said first polymer layer has a thickness greater than that of said passivation layer, greater than that of said first dielectric layer and greater than that of said second dielectric layer; and

a second metal layer on said first polymer layer and on said second contact point, wherein said second metal layer is connected to said second contact point through said second opening, wherein said second metal layer has a thickness greater than 0.6 micrometers, greater than that of said first circuit layer and greater than that of said second circuit layer, and wherein said second metal layer comprises a second titanium-containing layer, a second copper layer over said second titanium-containing layer, a nickel-containing layer on said second copper layer, and a gold layer on said nickel-containing layer.

2. The chip of claim 1, wherein said first metal layer is directly on said passivation layer.

3. The chip of claim 1, wherein said first titanium-containing layer comprises a titanium-tungsten alloy.

4. The chip of claim 1, wherein said first titanium-containing layer comprises titanium nitride.

5. The chip of claim 1, wherein said first polymer layer comprises polyimide.

6. The chip of claim 1, wherein said second titanium-containing layer comprises a titanium-tungsten alloy.

7. The chip of claim 1, wherein said second titanium-containing layer comprises titanium nitride.

8. The chip of claim 1 further comprising a second polymer layer on said second metal layer.

9. The chip of claim 1, wherein said second metal layer has an area used to be connected to a tin-containing solder.

10. The chip of claim 1, wherein said second metal layer has an area used to be wirebonded thereto.

11. The chip of claim 1, wherein said first contact point comprises at least an area directly over at least a portion of said multiple MOS devices.

12. The chip of claim 1, wherein said first contact point comprises at least an area directly under at least a portion of said second metal layer.

13. A chip comprising:

a silicon substrate;

multiple MOS devices in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first circuit layer and a second circuit layer over said first circuit layer, and wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second circuit layers;

a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said metallization structure and exposes said first contact point, wherein said first contact point comprises at least an area directly over at least a portion of said multiple MOS devices, wherein said passivation layer has a thickness greater than 0.35 micrometers, and wherein said passivation layer comprises a nitride layer;

a first metal layer over said passivation layer and on said first contact point, wherein said first metal layer is connected to said first contact point through said first opening, wherein said first metal layer has a thickness greater than 0.6 micrometers, greater than that of said first circuit layer and greater than that of said second circuit layer, and wherein said first metal layer comprises a first titanium-containing layer and a first copper layer over said first titanium-containing layer;

a first polymer layer over said passivation layer and over said first metal layer, wherein a second opening in said first polymer layer is over a second contact point of said first metal layer and exposes said second contact point, and wherein said first polymer layer has a thickness greater than that of said passivation layer, greater than that of said first dielectric layer and greater than that of said second dielectric layer;

a second metal layer on said first polymer layer and on said second contact point, wherein said second metal layer is connected to said second contact point through said second opening, wherein said second metal layer has a thickness greater than 0.6 micrometers, greater than that of said first circuit layer and greater than that of said second circuit layer, wherein said second metal layer comprises a second titanium-containing layer, a second copper layer over said second titanium-containing layer, and a nickel-containing layer on said second copper layer, and wherein said second metal layer comprises at least a portion directly over at least an area of said first contact point; and

a tin-containing solder over said second metal layer, wherein said tin-containing solder is connected to said first contact point through said first and second metal layers.

14. The chip of claim 13, wherein said first metal layer is directly on said passivation layer.

15. The chip of claim 13, wherein said first titanium-containing layer comprises a titanium-tungsten alloy.

16. The chip of claim 13, wherein said first titanium-containing layer comprises titanium nitride.

17. The chip of claim 13, wherein said first polymer layer comprises polyimide.

18. The chip of claim 13, wherein said second titanium-containing layer comprises a titanium-tungsten alloy.

19. The chip of claim 13, wherein said second titanium-containing layer comprises titanium nitride.

20. The chip of claim 13 further comprising a second polymer layer on said second metal layer.