LIGHTING SYSTEM WITH POWER FACTOR CORRECTION CONTROL DATA DETERMINED FROM A PHASE MODULATED SIGNAL

• US 20080224629A1
• Filed: 03/12/2008
• Published: 09/18/2008
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Signify Holding B.V. (Signify N.V.)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Melanson, John L.
• Granted Patent: US 8,174,204 B2
• Time in Patent Office: Days
• US Class Current: 315/247
• CPC Class Codes: H05B 45/355 Power factor correction [PFC]; Reactive power compensation
• CPC Class Codes: H05B 45/38 using boost topology
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
• CPC Class Codes: Y10S 315/04 Dimming circuit for fluorescent lamps

Abstract

A light emitting diode (LED) lighting system includes a power factor correction (PFC) controller that determines at least one power factor correction control parameter from phase delays of a phase modulated signal. In at least one embodiment, a peak voltage of the phase modulated signal is a PFC control parameter used bit the PFC controller to control power factor correction and generation of a link voltage by a PFC LED driver circuit. The phase delays are related to a peak voltage of the phase modulated signal. Thus, in at least one embodiment, detecting the phase delay in one or more cycles of the phase modulated signal allows the PFC controller to determine the peak voltage of the phase modulated signal.

Claims

1. A light emitting diode (LED) lighting system comprising:

a power factor correction (PFC) controller comprising;

an input to receive a phase delay signal indicating a phase delay of a phase modulated dimmer signal; and

a digital signal processor, coupled to the input, to receive the phase delays signal and determine a PFC control operating parameter from the phase delay signal and to generate a PFC switch control signal using the determined operating parameter.

2. The LED lighting system of claim 1 further comprising:

a time-based phase delay detector to detect the phase delays of the phase modulated signal and generate the phase delay signal as a digital signal.

3. The LED lighting system of claim 1 wherein the digital signal processor is further configured to execute a control signal state algorithm to determine a pulse width of the PFC switch control signal.

4. The LED lighting system of claim 1 wherein the operating parameter is a peak voltage of the phase modulated dimmer signal.

5. The LED lighting system of claim 1 wherein the phase delay signal indicates a dimming level and the PFC controller is further configured to generate a PFC switch control signal to cause a PFC LED driver circuit to respond to the dimming level indicated by the signal without decreasing an effective resistance of the PFC LED driver circuit, as perceived by a voltage source of the PFC LED driver circuit, as the dimming level indicated by the signal increases.

6. The LED lighting system of claim 1 wherein the PFC controller is further configured to generate a duty cycle modulated control signal to control a regulated link voltage of a PFC LED driver circuit and to decrease the link voltage when a duty cycle of the control signal decreases to a value between zero and a duty cycle threshold value.

7. The LED lighting system of claim 1 wherein the PFC controller is further configured to generate approximately constant pulse widths for the PFC switch control signal during each cycle of phase modulated signal when a duty cycle of PFC switch control signal is below a predetermined threshold.

8. The LED lighting system of claim 1 wherein the PFC controller is further configured to generate pulses for the PFC switch control signal during the phase delays of the phase modulated signal, wherein the pulse widths and duty cycles of the pulses of the PFC switch control signal generated during the phase delays are sufficient to attenuate ripple of the phase modulated signal during the phase delays of phase modulated signal.

9. The LED lighting system of claim 8 wherein the pulses of PFC switch control signal generated during the phase delays have a period significantly greater than a period of the pulses of the PFC switch control signal during an active period of phase modulated signal.

10. A method of controlling a light emitting diode (LED) lighting system, the method comprising:

receiving a phase delay signal indicating a phase delay of a phase modulated dimmer signal;

determining a PFC control operating parameter from the phase delay signal using a digital signal processor; and

generating a PFC switch control signal using the determined operating parameter.

11. The method of claim 10 further comprising:

detecting the phase delay of the phase modulated signal using a time-based phase delay detector; and

generating the phase delay signal as a digital signal.

12. The method of claim 10 further comprising:

executing a control signal state algorithm to determine a pulse width of the PFC switch control signal.

13. The method of claim 10 wherein the operating parameter is a peak voltage of the phase modulated dimmer signal.

14. The method of claim 10 wherein the phase delay signal indicates a dimming level, the method further comprising:

generating a power factor correction control signal to cause a PFC LED driver circuit to respond to the dimming level indicated by the signal without decreasing an effective resistance of the PFC load driver circuit, as perceived by a voltage source of the PFC load driver circuit as the dimming level indicated by the signal increases.

15. The method of claim 10 further comprising:

generating a duty cycle modulated control signal to control a regulated link voltage of a PFC LED driver circuit; and

decreasing the link voltage when a duty cycle of the control signal decreases to a value between zero and a duty cycle threshold value.

16. The method of claim 10 further comprising:

generating approximately constant pulse widths for the PFC switch control signal during each cycle of phase modulated signal when a duty cycle of PFC switch control signal is below a predetermined threshold.

17. The method of claim 10 further comprising:

generating pulses for the PFC switch control signal during the phase delays of the phase modulated signal, wherein the pulse widths and duty cycles of the pulses of the PFC switch control signal generated during the phase delays are sufficient to attenuate ripple of the phase modulated signal during the phase delays of phase modulated signal.

18. The method of claim 17 wherein the pulses of PFC switch control signal generated during the phase delays have a period significantly greater than a period of the pulses of the PFC switch control signal during an active period of phase modulated signal.

19. A light emitting diode (LED) lighting system comprising:

a power factor correction (PFC) controller to receive a signal indicating a dimming level and to generate a PFC switch control signal to cause a PFC LED driver circuit to respond to the dimming level indicated by the signal without decreasing an effective resistance of the PFC load driver circuit, as perceived by a voltage source of the PFC load driver circuit, as the dimming level indicated by the signal increases.

20. The lighting system of claim 19 wherein the PFC controller is further configured to decrease a duty cycle of the PFC switch control signal as the dimming level decreases until the dimming level reaches a dimming level threshold and to keep the duty cycle of the PFC switch control signal approximately constant for dimming levels below the dimming level threshold.

21. The lighting system of claim 19 wherein the PFC controller is further configured to increase the effective resistance of the PFC load driver circuit as the dimming level indicated by the dimming signal decreases.

23. The method of claim 19 further comprising:

decreasing a duty cycle of the PFC switch control signal as the dimming level decreases until the dimming level decreases to a dimming level threshold; and

keeping the duty cycle of the PFC switch control signal approximately constant for dimming levels below the dimming level threshold.

24. The method of claim 19 further comprising:

increasing the effective resistance of the PFC load driver circuit as the dimming level indicated by the dimming signal decreases.

22. A method of controlling a light emitting diode (LED) lighting system, the method comprising:

receiving a signal indicating a dimming level; and

generating a power factor correction control signal to cause a PFC LED driver circuit to respond to the dimming level indicated by the signal without decreasing an effective resistance of the PFC load driver circuit, as perceived by a voltage source of the PFC load driver circuit, as the dimming level indicated by the signal increases.

25. A light emitting diode (LED) lighting system comprising:

a power factor correction (PFC) controller to generate a duty cycle modulated control signal to control a regulated link voltage of a PFC LED driver circuit and to decrease the link voltage when a duty cycle of the control signal decreases to a value between zero and a duty cycle threshold value.

26. The LED lighting system of claim 25 wherein the PFC LED driver circuit is configured to operate from a mains voltage, and the PFC controller is configured to decrease the link voltage to approximately equal to the mains voltage.

27. The LED lighting system of claim 25 wherein the duty cycle threshold value is a member of the group consisting of 0.5 and between 0.25 and 0.5.

28. A method of controlling a light emitting diode (LED) lighting system, the method comprising:

generating a duty cycle modulated control signal to control a regulated link voltage of a PFC LED driver circuit; and

decreasing the link voltage when a duty cycle of the control signal decreases to a value between zero and a duty cycle threshold value.

29. The method of claim 28 wherein the PFC LED driver circuit is configured to operate from a mains voltage, the method further comprising:

decreasing the link voltage to approximately equal to the mains voltage.

30. The method of claim 28 wherein the duty cycle threshold value is a member of the group consisting of 0.5 and between 0.25 and 0.5.

31. A light emitting diode (LED) lighting system comprising:

a power factor correction (PFC) controller comprising;

an input to receive a phase delay signal indicating a phase delay of a phase modulated dimmer signal; and

wherein the PFC controller is configured to receive the phase delay signal and to generate pulses for the PFC switch control signal during the phase delays of the phase modulated signal, wherein the pulse widths and duty cycles of the pulses of the PFC switch control signal generated during the phase delays are sufficient to attenuate ripple of the phase modulated signal during the phase delays of phase modulated signal.

32. A method of controlling a light emitting diode (LED) lighting system, the method comprising:

receiving a phase delay signal indicating a phase delay of a phase modulated dimmer signal;

generating pulses for a PFC switch control signal during the phase delays of the phase modulated signal, wherein the pulse widths and duty cycles of the pulses of the PFC switch control signal generated during the phase delays are sufficient to attenuate ripple of the phase modulated signal during the phase delays of phase modulated signal.