Semiconductor device and manufacturing method thereof

• US 20080224940A1
• Filed: 03/07/2008
• Published: 09/18/2008
• Est. Priority Date: 03/13/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tsurume, Takuya, Sugiyama, Eiji, Dozen, Yoshitaka, Ohtani, Hisashi
• Granted Patent: US 7,808,098 B2
• Time in Patent Office: Days
• US Class Current: 343/873
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/07811 Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01Q 1/2225 used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00

Abstract

The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.

Claims

1. A semiconductor device comprising:

a semiconductor element; and

a sealing layer with a thickness greater than or equal to 10 μ

m and less than or equal to 100 μ

m, including a fibrous body and an organic resin, the fibrous body being impregnated with the organic resin,

wherein the sealing layer is fixed to at least one of surfaces of the semiconductor element.

2. The semiconductor device according to claim 1, wherein the fibrous body is one of a woven fabric and an unwoven fabric.

3. The semiconductor device according to claim 1, wherein the organic resin includes one of a thermosetting resin and a thermoplastic resin.

4. The semiconductor device according to claim 3, wherein the thermosetting resin is one of an epoxy resin, an unsaturated polyester resin, a polyimide resin, a bismaleimide-triazine resin, and a cyanate resin.

5. The semiconductor device according to claim 3, wherein the thermoplastic resin is one of a polyphenylene oxide resin, a polyetherimide resin, and a fluorine resin.

6. The semiconductor device according to claim 1, wherein the semiconductor element is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

7. The semiconductor device according to claim 1, further comprising an antenna between the semiconductor element and the sealing layer, the antenna being electrically connected to the semiconductor element.

8. A semiconductor device comprising:

an element substrate with a thickness greater than or equal to 1 μ

m and less than or equal to 80 μ

m, including an active element and an insulating layer, the active element being formed using one of a single crystal semiconductor substrate and an SOI substrate and being covered with the insulating layer; and

a sealing layer with a thickness greater than or equal to 10 μ

m and less than or equal to 100 μ

m, including a fibrous body and an organic resin, the fibrous body being impregnated with the organic resin,

wherein the sealing layer is fixed to at least one of surfaces of the element substrate.

9. The semiconductor device according to claim 8, wherein the fibrous body is one of a woven fabric and an unwoven fabric.

10. The semiconductor device according to claim 8, wherein the organic resin includes one of a thermosetting resin and a thermoplastic resin.

11. The semiconductor device according to claim 10, wherein the thermosetting resin is one of an epoxy resin, an unsaturated polyester resin, a polyimide resin, a bismaleimide-triazine resin, and a cyanate resin.

12. The semiconductor device according to claim 10, wherein the thermoplastic resin is one of a polyphenylene oxide resin, a polyetherimide resin, and a fluorine resin.

13. The semiconductor device according to claim 8, wherein the active element is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

14. The semiconductor device according to claim 8, further comprising an antenna between the element substrate and the sealing layer, the antenna being electrically connected to the active element of the element substrate.

15. A semiconductor device comprising:

an element substrate with a thickness greater than or equal to 1 μ

m and less than or equal to 80 μ

m, including an active element and an insulating layer, the active element being formed using one of a single crystal semiconductor substrate and an SOI substrate and being covered with the insulating layer; and

a sealing layer with a thickness greater than or equal to 10 μ

m and less than or equal to 100 μ

m, including a fibrous body and an organic resin, the fibrous body being impregnated with the organic resin and having a plurality of warp yarns and a plurality of weft yarns each formed by bundling a plurality of single yarns,

wherein the sealing layer is fixed to at least one of surfaces of the element substrate.

16. The semiconductor device according to claim 15, wherein the fibrous body is one of a woven fabric and an unwoven fabric.

17. The semiconductor device according to claim 15, wherein each of a distance between the plurality of warp yarns and a distance between the plurality of weft yarns is greater than or equal to 0.01 mm and less than or equal to 0.2 mm.

18. The semiconductor device according to claim 15, wherein the organic resin includes one of a thermosetting resin and a thermoplastic resin.

19. The semiconductor device according to claim 18, wherein the thermosetting resin is one of an epoxy resin, an unsaturated polyester resin, a polyimide resin, a bismaleimide-triazine resin, and a cyanate resin.

20. The semiconductor device according to claim 18, wherein the thermoplastic resin is one of a polyphenylene oxide resin, a polyetherimide resin, and a fluorine resin.

21. The semiconductor device according to claim 15, wherein the active element is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

22. The semiconductor device according to claim 15, further comprising an antenna between the element substrate and the sealing layer, the antenna being electrically connected to the active element of the element substrate.

23. A manufacturing method of a semiconductor device comprising the steps of:

forming a semiconductor element;

providing, over the semiconductor element, a structure body in which a fibrous body is impregnated with an organic resin; and

performing heating and pressure bonding to form, over the semiconductor element, a sealing layer which includes the fibrous body and the organic resin with which the fibrous body is impregnated.

24. The manufacturing method of a semiconductor device according to claim 23, wherein the semiconductor element is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

25. A manufacturing method of a semiconductor device comprising the steps of:

forming an element substrate having an active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate and an insulating layer which covers the active element;

providing, over the element substrate, a structure body in which a fibrous body is impregnated with an organic resin; and

performing heating and pressure bonding to form, over the element substrate, a sealing layer which includes the fibrous body and the organic resin with which the fibrous body is impregnated.

26. The manufacturing method of a semiconductor device according to claim 25, wherein the active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

27. A manufacturing method of a semiconductor device comprising the steps of:

forming an element substrate having an active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate and an insulating layer which covers the active element;

providing, over one surface of the element substrate, a first structure body in which a first fibrous body is impregnated with a first organic resin;

performing heating and pressure bonding to form, over the one surface of the element substrate, a first sealing layer which includes the first fibrous body and the first organic resin with which the first fibrous body is impregnated;

providing, over the other surface of the element substrate, a second structure body in which a second fibrous body is impregnated with a second organic resin; and

performing heating and pressure bonding to form, over the other surface of the element substrate, a second sealing layer which includes the second fibrous body and the second organic resin with which the second fibrous body is impregnated.

28. The manufacturing method of a semiconductor device according to claim 27, wherein the active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

29. A manufacturing method of a semiconductor device comprising the steps of:

forming an element substrate having an active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate, an insulating layer which covers the active element, and a wiring;

providing, over the element substrate, a structure body in which a fibrous body is impregnated with an organic resin;

performing heating and pressure bonding to form, over the element substrate, a sealing layer which includes the fibrous body and the organic resin with which the fibrous body is impregnated;

removing part of the sealing layer and forming a connection terminal which is connected to the wiring; and

attaching a substrate having an antenna to the sealing layer to electrically connect the connection terminal and the antenna.

30. The manufacturing method of a semiconductor device according to claim 29, wherein the active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

31. A manufacturing method of a semiconductor device comprising the steps of:

forming an element substrate having an active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate, an insulating layer which covers the active element, and a wiring;

providing, over one surface of the element substrate, a first structure body in which a first fibrous body is impregnated with a first organic resin;

performing heating and pressure bonding to form, over the one surface of the element substrate, a first sealing layer which includes the first fibrous body and the first organic resin with which the first fibrous body is impregnated;

removing part of the first sealing layer and forming a connection terminal which is connected to the wiring;

attaching a substrate having an antenna to the first sealing layer to electrically connect the connection terminal and the antenna;

providing, over the other surface of the element substrate, a second structure body in which a second fibrous body is impregnated with a second organic resin; and

performing heating and pressure bonding to form, over the other surface of the element substrate, a second sealing layer which includes the second fibrous body and the second organic resin with which the second fibrous body is impregnated.

32. The manufacturing method of a semiconductor device according to claim 31, wherein the active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate is one or more of a MOS transistor, a nonvolatile memory element, and a diode.

33. A manufacturing method of a semiconductor device comprising the steps of:

forming an element substrate having an active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate, an insulating layer which covers the active element, a first wiring, and a second wiring;

providing, over one surface of the element substrate, a first structure body in which a first fibrous body is impregnated with a first organic resin;

performing heating and pressure bonding to form, over the one surface of the element substrate, a first sealing layer which includes the first fibrous body and the first organic resin with which the first fibrous body is impregnated;

removing part of the first sealing layer and forming a first connection terminal which is connected to the first wiring;

attaching a first substrate having a first antenna to the first sealing layer to electrically connect the first connection terminal and the first antenna;

providing, over the other surface of the element substrate, a second structure body in which a second fibrous body is impregnated with a second organic resin;

performing heating and pressure bonding to form, over the other surface of the element substrate, a second sealing layer including the second fibrous body and the second organic resin with which the second fibrous body is impregnated;

removing part of the second sealing layer and forming a second connection terminal which is connected to the second wiring; and

attaching a second substrate having a second antenna to the second sealing layer to electrically connect the second connection terminal and the second antenna.

34. The manufacturing method of a semiconductor device according to claim 33, wherein the active element which is formed using one of a single crystal semiconductor substrate and an SOI substrate is one or more of a MOS transistor, a nonvolatile memory element, and a diode.