Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array

• US 20080225594A1
• Filed: 03/13/2008
• Published: 09/18/2008
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Hsu, Fu-Chang
• Granted Patent: US 7,830,713 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the serially connected select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected select transistor. The pair of serially connected top select transistors is connected to a first of two associated bit lines. Optionally, the NAND nonvolatile memory strings further is connected a pair of serially connected bottom select transistors that is connected to the second associated bit line.

Claims

1. A nonvolatile memory structure comprising:

a plurality of dual-sided charge-trapping nonvolatile memory cells connected in a NAND series string; and

a pair of serially connected top select transistors,

wherein each of the pair of serially connected top select transistors have a first source/drain and each of the first source/drains are connected together,

wherein a first of the serially connected top select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected top select transistor,

wherein a second source/drain of one of the pair of serially connected transistors is connected to a top dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells, and

wherein a second source/drain of another of the serially connected transistors is connected to a first of two bit lines associated with the NAND series string nonvolatile memory structure.

2. The nonvolatile memory structure of claim 1 further comprising a bottom select transistor having a first source/drain connected to a bottom dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells and a second source/drain connected to a second of the two bit lines associated with the NAND series string nonvolatile memory structure.

3. The nonvolatile memory structure of claim 1 further comprising a pair of serially connected bottom select transistors,

wherein each of the pair of serially connected bottom select transistors has a first source/drain and each of the first source/drains are connected together,

wherein a first of the serially connected bottom select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a second non-implanted serially connected bottom select transistor,

wherein a second source/drain of one of the serially connected transistors is connected to a bottom dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells, and

wherein a second source/drain of another of the serially connected bottom transistors is connected to a second of the two bit lines associated with the NAND series string nonvolatile memory structure.

4. The nonvolatile memory structure of claim 1 wherein both of the pair of serially connected top select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected top select transistors and a second select voltage applied to a gate of the other non-implanted pair of serially connected top select transistors are greater than the threshold voltages of the pair of serially connected top select transistors to connect the top dual-sided charge-trapping nonvolatile memory cell to the first of two bit lines with the NAND series string.

5. The nonvolatile memory structure of claim 3 wherein both of the pair of serially connected bottom select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected bottom select transistors and a second select voltage applied to a gate of the other non-implanted pair of serially connected bottom select transistors are greater than the threshold voltages of the pair of serially connected bottom select transistors to connect the bottom dual-sided charge-trapping nonvolatile memory cell to the first of two bit lines with the NAND series string.

6. The nonvolatile memory structure of claim 1 wherein the implant is an acceptor impurity and adjusts the threshold voltage of the implanted one serially connected top select transistor to a larger positive voltage.

7. The nonvolatile memory structure of claim 6 wherein the acceptor impurity is boron.

8. The nonvolatile memory structure of claim 6 wherein the larger positive voltage is approximately +4.0V.

9. The nonvolatile memory structure of claim 1 wherein the implant is a donor impurity and adjusts the threshold voltage of the implanted one serially connected select transistor to a larger negative voltage.

10. The nonvolatile memory structure of claim 9 wherein the donor impurity is phosphorus.

11. The nonvolatile memory structure of claim 9 wherein the larger negative voltage is approximately −

4.0V.

12. The nonvolatile memory structure of claim 3 wherein the implant is an acceptor impurity and adjusts the threshold voltage of the implanted one serially connected bottom select transistor to a larger positive voltage.

13. The nonvolatile memory structure of claim 12 wherein the acceptor impurity is boron.

14. The nonvolatile memory structure of claim 12 wherein the larger positive voltage is approximately +4.0V.

15. The nonvolatile memory structure of claim 3 wherein the implant is a donor impurity and adjusts the threshold voltage of the implanted one serially connected select transistor to a larger negative voltage.

16. The nonvolatile memory structure of claim 15 wherein the donor impurity is phosphorus.

17. The nonvolatile memory structure of claim 15 wherein the larger negative voltage is approximately −

4.0V.

18. A nonvolatile memory array comprising:

a plurality of nonvolatile memory cells arranged in row and columns such that groups of the nonvolatile memory cells are serially connected to form NAND nonvolatile memory strings where each column includes at least one of the NAND nonvolatile memory strings, each of the NAND nonvolatile memory strings further comprising;

a pair of serially connected top select transistors,

wherein the pair of serially connected top select transistors each has a first source/drain with the two first source/drains of the pair of serially connected top select transistors being connected together,

wherein a first of the serially connected top select transistors has an implant to make a threshold voltage of the implanted first serially connected top select transistor different from a non-implanted second serially connected top select transistor,

wherein a second source/drain of one top select transistor of the pair of serially connected top select transistors is connected to a top dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells, and

a plurality of bit lines, placed within the nonvolatile memory array such that each the bit lines is associated with at least one of the columns of the plurality of NAND nonvolatile memory strings and each of the columns of the plurality of NAND nonvolatile memory strings is associated with a pair of bit lines.

wherein a second source/drain of a top select transistor of the pair of serially connected top select transistors is connected to a first of the two bit lines associated with the NAND series string nonvolatile memory structure.

19. The nonvolatile memory array of claim 18 wherein each NAND nonvolatile memory string further comprises a bottom select transistor having a first source/drain connected to a bottom dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells and a second source/drain connected to a second of the two bit lines associated with the NAND series string nonvolatile memory structure.

20. The nonvolatile memory array of claim 18 wherein each NAND nonvolatile memory string further comprises a pair of serially connected bottom select transistors,

wherein each of the pair of serially connected bottom select transistors has a first source/drain connected together;

wherein a first of the serially connected bottom select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from the other non-implanted serially connected bottom select transistor; and

wherein a second source/drain of one of the serially connected transistors is connected to a bottom dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells.

21. The nonvolatile memory array of claim 18 wherein both of the pair of serially connected top select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected top select transistors and a second select voltage applied to a gate of other non-implanted transistor of the serially connected top select transistors are greater than the threshold voltages pair of serially connected top select transistors to connect the top dual-sided charge-trapping nonvolatile memory cell to the first of two bit lines associated with the NAND series string nonvolatile memory structure.

22. The nonvolatile memory array of claim 18 wherein both of the pair of serially connected bottom select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected bottom select transistors and a second select voltage applied to a gate of other non-implanted pair of serially connected bottom select transistors are greater than the threshold voltages pair of serially connected bottom select transistors to connect the bottom dual-sided charge-trapping nonvolatile memory cell to the second of two bit lines associated with the NAND series string nonvolatile memory structure.

23. The nonvolatile memory array of claim 18 wherein the implant is an acceptor impurity and adjusts the threshold voltage of the implanted one serially connected top select transistor to a larger positive voltage.

24. The nonvolatile memory array of claim 23 wherein the acceptor impurity is boron.

25. The nonvolatile memory array of claim 23 wherein the larger positive voltage is approximately +4.0V.

26. The nonvolatile memory array of claim 23 wherein the implant is a donor impurity and adjusts the threshold voltage of the implanted one serially connected top select transistor to a larger negative voltage.

27. The nonvolatile memory array of claim 29 wherein the donor impurity is phosphorus.

28. The nonvolatile memory array of claim 29 wherein the larger negative voltage is approximately −

4.0V.

29. The nonvolatile memory array of claim 20 wherein the implant is an acceptor impurity and adjusts the threshold voltage of the implanted one serially connected bottom select transistor to a larger positive voltage.

30. The nonvolatile memory array of claim 29 wherein the acceptor impurity is boron.

31. The nonvolatile memory array of claim 29 wherein the larger positive voltage is approximately +4.0V.

32. The nonvolatile memory array of claim 20 wherein the implant is a donor impurity and adjusts the threshold voltage of the implanted one serially connected bottom select transistor to a larger negative voltage.

33. The nonvolatile memory array of claim 32 wherein the acceptor impurity is boron.

34. The nonvolatile memory array of claim 32 wherein the larger negative voltage is approximately 4.0V.

35. A method of forming a nonvolatile memory structure comprising the steps of:

forming a plurality of dual-sided charge-trapping nonvolatile memory cells;

connecting a plurality of dual-sided charge-trapping nonvolatile memory cells in a NAND series string;

forming a pair of serially connected top select transistors;

connecting together both first source/drain of the pair of serially connected top select transistors;

implanting a first of the serially connected top select transistors to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected top select transistor;

connecting a second source/drain of one of the pair of serially connected transistors to a top dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells; and

connecting a second source/drain of another of the serially connected transistors to a first of two bit lines associated with the NAND series string nonvolatile memory structure.

36. The method of forming a nonvolatile memory structure of claim 35 further comprising the steps of:

forming a bottom select transistor;

connecting a first source/drain of the bottom select transistor to a bottom dual-sided charge-trapping nonvolatile memory cell of the NAND series string of dual-sided charge-trapping nonvolatile memory cells; and

connecting a second source/drain to a second of the two bit lines associated with the NAND series string nonvolatile memory structure.

37. The method of forming a nonvolatile memory structure of claim 35 further comprising the steps of:

forming a pair of serially connected bottom select transistors;

connecting together a first source/drain of each of the pair of serially connected bottom select transistors;

implanting a first of the serially connected bottom select transistors to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected bottom select transistor;

connecting a second source/drain of one of the serially connected transistors to a bottom dual-sided charge-trapping nonvolatile memory cell of the NAND series string; and

connecting a second source/drain of another of the serially connected bottom transistors to a second of the two bit lines associated with the NAND series string.

38. The method of forming a nonvolatile memory structure of claim 35 wherein both of the pair of serially connected top select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected top select transistors and a second select voltage applied to a gate of the other non-implanted pair of serially connected top select transistors are greater than the threshold voltages of the pair of serially connected top select transistors to connect the top dual-sided charge-trapping nonvolatile memory cell to the first of two bit lines with the NAND series string.

39. The method of forming a nonvolatile memory structure of claim 37 wherein both of the pair of serially connected bottom select transistors are turned on only when a first select voltage applied to a gate of the one implanted transistor of the pair of serially connected bottom select transistors and a second select voltage applied to a gate of the other non-implanted pair of serially connected bottom select transistors are greater than the threshold voltages of the pair of serially connected bottom select transistors to connect the bottom dual-sided charge-trapping nonvolatile memory cell to the first of two bit lines with the NAND series string.

40. The method of forming a nonvolatile memory structure of claim 35 wherein implanting a first of the serially connected top select transistors comprises the step of implanting an acceptor impurity and adjusting the threshold voltage of the implanted one serially connected top select transistor to a larger positive voltage.

41. The method of forming a nonvolatile memory structure of claim 40 wherein the acceptor impurity is boron.

42. The method of forming a nonvolatile memory structure of claim 40 wherein the larger positive voltage is approximately +4.0V.

43. The method of a forming a nonvolatile memory structure of claim 35 wherein implanting a first of the serially connected top select transistors comprises the steps of implanting a donor impurity and adjusting the threshold voltage of the implanted one serially connected select transistor to a larger negative voltage.

44. The method of a forming a nonvolatile memory structure of claim 43 wherein the donor impurity is phosphorus.

45. The method of forming a nonvolatile memory structure of claim 43 wherein the larger negative voltage is approximately −

4.0V.

46. The method of forming a nonvolatile memory structure of claim 37 wherein the implanting a first of the serially connected bottom select transistors comprises the step of implanting an acceptor impurity and adjusting the threshold voltage of the implanted one serially connected bottom select transistor to a larger positive voltage.

47. The method of forming a nonvolatile memory structure of claim 46 wherein the acceptor impurity is boron.

48. The method of forming a nonvolatile memory structure of claim 46 wherein the larger positive voltage is approximately +4.0V.

49. The method of forming a nonvolatile memory structure of claim 37 wherein implanting a first of the serially connected bottom select transistors comprises the step of implanting a donor impurity and adjusting the threshold voltage of the implanted one serially connected select transistor to a larger negative voltage.

50. The method of forming a nonvolatile memory structure of claim 49 wherein the donor impurity is phosphorus.

51. The method of forming a nonvolatile memory structure of claim 49 wherein the larger negative voltage is approximately −

4.0V.