PROTOCOL-AGNOSTIC AUTOMATIC RATE NEGOTIATION FOR HIGH-SPEED SERIAL INTERFACE IN A PROGRAMMABLE LOGIC DEVICE

• US 20080225933A1
• Filed: 03/16/2007
• Published: 09/18/2008
• Est. Priority Date: 03/16/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, Chan, Allen, Shumarayev, Sergey
• Granted Patent: US 8,831,140 B2
• Time in Patent Office: Days
• US Class Current: 375/225
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H04L 5/1446 of transmission speed
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.

Claims

1. A method for determining a data rate in a programmable logic device serial interface channel operating at a clock rate, said method comprising:

monitoring said channel for occurrence of single-bit transitions; and

on detection of a plural number of said single-bit transitions within a predetermined duration, concluding that said data rate is substantially a multiple of said clock rate.

2. The method of claim 1 further comprising:

assuming initially that said data rate is substantially equal to said clock rate; and

in absence of said detection of said plural number of said single-bit transitions, concluding that said initial assumption is correct.

3. The method of claim 1 wherein said multiple is substantially equal to said plural number.

4. The method of claim 3 wherein each of said multiple and said plural number is equal to two.

5. The method of claim 1 wherein said predetermined duration is equal to a predetermined number of clock cycles.

6. The method of claim 1 wherein said detection is based on phase transitions.

7. A serial interface for use in a programmable logic device, said serial interface having a channel operating at a clock rate and comprising:

a receiver portion operable in both a first mode in which data is received at a data rate substantially equal to said clock rate and a second mode in which data is received at a data rate substantially equal to an integer multiple of said clock rate; and

rate negotiation circuitry for determining which of said first and second modes said receiver portion is operating in, based on a number of single-bit transitions detected in said received data within a predetermined duration.

8. The serial interface of claim 7 further comprising:

clock data recovery circuitry that extracts, from said received data, a clock at said clock rate;

wherein;

said clock data recovery circuitry cooperates with said rate negotiation circuitry to determine which of said modes said receiver portion is operating in.

9. The serial interface of claim 8 wherein:

said clock data recovery circuitry comprises a phase detector; and

said phase detector detects said single-bit transitions.

10. The serial interface of claim 9 wherein said phase detector is a bang-bang phase detector.

11. The serial interface of claim 10 wherein:

said bang-bang phase detector comprises;

four first-stage registers, each of which is respectively clocked by a respective quadrature phase of said recovered clock, said four first-stage registers outputting four respective first-stage signals representing delayed phases of said received data, and

six second-stage registers, said six second-stage registers comprising a first group of three registers clocked by a second (90°

) quadrature phase of said recovered clock, and a second group of three registers clocked by a fourth (270°

) quadrature phase of said recovered clock;

said registers in said first group receive first, second and third ones of said delayed phases of said received data;

said registers in said second group receive third, fourth and first ones of said delayed phases of said received data; and

predetermined states of said six second-stage registers in one of two successive clock cycles signify to said rate negotiation circuitry that said receiver portion is operating in a particular one of said first and second modes.

12. A programmable logic device comprising the serial interface of claim 7.

13. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 12 coupled to the processing circuitry and the memory.

14. A printed circuit board on which is mounted a programmable logic device as defined in claim 12.

15. The printed circuit board defined in claim 14 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

16. The printed circuit board defined in claim 15 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

17. An automatic rate negotiation engine for use in a dedicated transceiver of a programmable logic device, said transceiver operating under an 8B/10B encoding scheme and including clock data recovery circuitry, said clock data recovery circuitry comprising a phase detector, said automatic rate negotiation engine comprising:

said phase detector, said phase detector receiving input data and a clock recovered by said clock data recovery circuitry;

rate decision logic receiving signals from said phase detector representing transitions in said input data, said rate decision logic determining a data rate of said transceiver from said signals representing transitions and outputting a decision signal; and

a line rate clock synthesizer receiving said recovered clock and said decision signal and synthesizing therefrom a line rate for said transceiver.

18. The automatic rate negotiation engine of claim 17 wherein said phase detector is a bang-bang phase detector.

19. The automatic rate negotiation engine of claim 17 wherein:

said input data is received under a particular protocol; and

said automatic rate negotiation engine operates based on said transitions without regard to said protocol.