METHOD AND SYSTEM OF PROVIDING A HIGH SPEED TOMLINSON-HARASHIMA PRECODER
First Claim
1. A method of processing a discrete time sampled sequence by a Tomlinson-Harashima Precoder (THP) comprising:
- receiving a first discrete time sampled sequence by an L-tap Tomlinson-Harashima Precoder (THP);
receiving a clock signal by said L-tap Tomlinson-Harashima Precoder (THP), said clock signal having a clock rate equal to one half the symbol rate of said discrete time sampled sequence;
using L state variables to express one or more outputs of said L-tap Tomlinson-Harashima Precoder (THP);
processing said first discrete time sampled sequence using L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal; and
outputting a second discrete time sampled sequence by said L-tap Tomlinson-Harashima Precoder.
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Abstract
Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.
10 Citations
30 Claims
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1. A method of processing a discrete time sampled sequence by a Tomlinson-Harashima Precoder (THP) comprising:
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receiving a first discrete time sampled sequence by an L-tap Tomlinson-Harashima Precoder (THP); receiving a clock signal by said L-tap Tomlinson-Harashima Precoder (THP), said clock signal having a clock rate equal to one half the symbol rate of said discrete time sampled sequence; using L state variables to express one or more outputs of said L-tap Tomlinson-Harashima Precoder (THP); processing said first discrete time sampled sequence using L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal; and outputting a second discrete time sampled sequence by said L-tap Tomlinson-Harashima Precoder. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An L-tap Tomlinson-Harashima Precoder (THP) comprising:
at least one circuitry for receiving a first discrete time sampled sequence;
said at least one circuitry for receiving a clock signal, wherein said clock rate is equal to one half the rate of the symbol rate of said first discrete time sampled sequence;
said at least one circuitry for receiving L coefficients, said at least one circuitry for using L state variables to express one or more outputs of said L-tap Tomlinson-Harashima Precoder (THP);
said at least one circuitry for processing said first discrete time sampled sequence using said L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal; and
said at least one circuitry for outputting a second discrete time sampled sequence.- View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An L-tap Tomlinson-Harashima Precoder (THP) comprising:
a single integrated circuit chip, said integrated circuit chip comprising; at least one circuitry for receiving a first discrete time sampled sequence, said at least one circuitry for receiving a clock signal, said clock rate equal to one half the rate of the symbol rate of said first discrete time sampled sequence, said at least one circuitry for using L state variables to express one or more outputs of said Tomlinson-Harashima Precoder (THP), said at least one circuitry for processing said first discrete time sampled sequence using L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal, and said at least one circuitry for outputting a second discrete time sampled sequence. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
Specification