Measurement of Overlay Offset in Semiconductor Processing

• US 20080227228A1
• Filed: 03/14/2007
• Published: 09/18/2008
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ke, Chih-Ming, Gau, Tsai-Sheng, Huang, Te-Chih
• Granted Patent: US 7,858,404 B2
• Time in Patent Office: Days
• US Class Current: 438/16
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14

Abstract

A method of semiconductor manufacturing including forming an overlay offset measurement target including a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have a first predetermined overlay offset. The target is irradiated. The reflectivity of the irradiated target is determined. An overlay offset for the first layer and the second layer is calculated using the determined reflectivity.

Claims

1. A method of semiconductor manufacturing, comprising:

forming an overlay offset measurement target including a first feature located on a first layer and a second feature located on a second layer, wherein the first feature and the second feature have a first predetermined overlay offset;

irradiating the target;

determining a reflectivity of the irradiated target; and

calculating an overlay offset for the first layer and the second layer using the determined reflectivity.

2. The method of claim 1, further comprising:

using the calculated overlay offset in determining whether to rework a wafer.

3. The method of claim 1, wherein the first predetermined overlay offset is between approximately 4 nanometers and 40 nanometers.

4. The method of claim 1, wherein the target further includes a third feature located on the first layer and a fourth feature located on the second layer, wherein the third feature and the fourth feature have a second predetermined overlay offset.

5. The method of claim 4, wherein determining the reflectivity includes determining a first reflectivity, wherein the first reflectivity includes the reflectivity of the first feature and the second feature of the irradiated target, and determining a second reflectivity, wherein the second reflectivity includes the reflectivity of the third feature and the fourth feature of the irradiated target.

6. The method of claim 4, wherein the second predetermined overlay offset is different than the first predetermined overlay offset.

7. The method of claim 1, wherein calculating an overlay offset includes determining a predetermined overlay offset that provides an actual overlay offset of approximately zero.

8. The method of claim 7, wherein the determining a predetermined overlay offset that provides an actual overlay offset of approximately zero includes determining a predetermined overlay offset that provides for greatest reflectivity.

9. A system for overlay offset measurement in semiconductor manufacturing, comprising:

a radiation source, wherein the radiation source is operable to irradiate an overlay offset measurement target;

a detector, wherein the detector is operable to detect reflectivity of the irradiated overlay offset measurement target; and

a calculation unit, wherein the calculation unit is operable to determine an overlay offset using the detected reflectivity.

10. The system of claim 9, wherein the radiation source and the detector are in-situ with a lithography system.

11. The system of claim 10, wherein the calculation unit determines the offset by comparing the detected reflectivity and the predetermined overlay offsets.

12. The system of claim 10, wherein the plurality of predetermined overlay offsets includes at least two different predetermined overlay offsets.

13. An overlay offset measurement target, comprising:

a first feature and a second feature having a first predetermined overlay offset; and

a third feature and a fourth feature having a second predetermined overlay offset, wherein the first predetermined overlay offset and the second predetermined overlay offset are different.

14. The target of claim 13, further comprising:

a fifth feature and a sixth feature having a third predetermined overlay offset.

15. The target of claim 14, wherein the third predetermined overlay offset is approximately zero.

16. The target of claim 13, wherein the first predetermined overlay offset and the second predetermined overlay offset are offsets of a substantially equivalent distance in opposite directions.

17. The target of claim 13, wherein the first feature and the third feature are on a first layer of a wafer and the second feature and the fourth feature are on a second layer of the wafer.

18. The target of claim 17, wherein the second feature and the fourth feature are fabricated of photoresist.

19. The target of claim 17, wherein the first layer and the second layer are adjacent layers on the wafer.

20. The target of claim 13, wherein the target is of sufficient size such that the target may be irradiated and a reflectivity of the irradiated target detected.