Method of assembling chips

• US 20080227237A1
• Filed: 05/29/2008
• Published: 09/18/2008
• Est. Priority Date: 10/25/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lin, Shih-Hsiung
• Granted Patent: US 8,021,921 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11822 by dipping, e.g. in a solder bath
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/1312 Antimony [Sb] as principal constituent
• CPC Class Codes: H01L 2224/13123 Magnesium [Mg] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

Claims

1. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip and a first tin-containing layer over said copper pillar, wherein said first tin-containing layer has a thickness less than that of said copper pillar;

providing a second tin-containing layer on a substrate, wherein said second tin-containing layer has a thickness less than said thickness of said copper pillar; and

joining said first tin-containing layer with said second tin-containing layer.

2. The method of claim 1, wherein said providing said copper pillar is performed with said providing said copper pillar over a pad in said chip, wherein said copper pillar has a transverse dimension less than that of said pad.

3. The method of claim 1, wherein said providing said first tin-containing layer is performed with said first tin-containing layer comprising silver.

4. The method of claim 1, wherein said providing said second tin-containing layer comprises a process comprising a screen-printing process.

5. The method of claim 1, wherein said providing said second tin-containing layer is performed with said second tin-containing layer comprising silver.

6. The method of claim 1, wherein said joining said first tin-containing layer with said second tin-containing layer comprises a reflow process.

7. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip and a tin-containing layer over said copper pillar, wherein said tin-containing layer has a thickness less than that of said copper pillar;

providing a gold-containing layer on a substrate, wherein said gold-containing layer has a thickness less than said thickness of said copper pillar; and

joining said tin-containing layer with said gold-containing layer.

8. The method of claim 7, wherein said providing said copper pillar is performed with said providing said copper pillar over a pad in said chip, wherein said copper pillar has a transverse dimension less than that of said pad.

9. The method of claim 7, wherein said providing said tin-containing layer is performed with said tin-containing layer comprising silver.

10. The method of claim 7, wherein said joining said tin-containing layer with said gold-containing layer comprises a reflow process.

11. A method for fabricating a chip package, comprising:

providing a metal bump on a chip, wherein said metal bump comprises a copper pillar over said chip;

providing a tin-containing layer on a substrate, wherein said tin-containing layer has a thickness greater than 15 micrometers and less than a thickness of said copper pillar; and

joining said metal bump with said tin-containing layer using a process comprising a reflow process.

12. The method of claim 11, wherein said providing said tin-containing layer is performed with said tin-containing layer comprising silver.

13. The method of claim 11, wherein said providing said tin-containing layer is performed with said tin-containing layer comprising silver and copper.

14. The method of claim 11, wherein said providing said tin-containing layer is performed with said tin-containing layer comprising lead.

15. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip and a first gold-containing layer over said copper pillar, wherein said first gold-containing layer has a thickness less than that of said copper pillar;

providing a second gold-containing layer on a substrate, wherein said second gold-containing layer has a thickness less than said thickness of said copper pillar; and

joining said first gold-containing layer with said second gold-containing layer.

16. The method of claim 15, wherein said providing said copper pillar is performed with said providing said copper pillar over a pad in said chip, wherein said copper pillar has a transverse dimension less than that of said pad.