PROCESSING APPARATUS AND CONTROL METHOD THEREOF

• US 20080228846A1
• Filed: 03/13/2008
• Published: 09/18/2008
• Est. Priority Date: 03/16/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: HONDOU, Mikio, Yoshida, Toshio, Kan, Ryuji
• Granted Patent: US 8,655,935 B2
• Time in Patent Office: Days
• US Class Current: 708/503
• CPC Class Codes: G06F 1/02 Digital function generators
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/548 Trigonometric functions; Co-ordinate transformations

Abstract

A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Claims

1. A processing apparatus comprising:

a register that stores operand data;

a register data reading section that reads operand data stored in the register;

a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data;

a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information; and

a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register or bypass data.

2. The processing apparatus according to claim 1, wherein the coefficient table in the processing apparatus stores only coefficient data of even number degrees for a mathematical function which is an even function and only coefficient data of odd number degrees for a mathematical function which is an odd function.

3. The processing apparatus according to claim 2, wherein the odd function in the processing apparatus is a sine function and the even function is a cosine function, and

the coefficient table set storage section has a coefficient table of the sine function and a coefficient table of the cosine function.

4. The processing apparatus according to claim 3, wherein when performing the sine function or the cosine function using a Taylor series operation, the processing apparatus chooses to use the coefficient table of the sine function or the coefficient table of the cosine function depending on the range of input arguments of the mathematical functions.

5. The processing apparatus according to claim 4, wherein when the input argument of the sine function or the cosine function is outside the range of −

π

/4 to +π

/4, the processing apparatus converts the input argument so that the input argument of the sine function or the cosine function falls within a range of −

π

/4 to +π

/4 and executes a Taylor series operation using the coefficient data of the coefficient table of the sine function or cosine function obtained by the input argument conversion.

6. The processing apparatus according to claim 1, the processing apparatus further comprising a selection and output section that receives coefficient data in the coefficient table set storage section read by the coefficient data reading section and data or bypass data read by the register data reading section as input and stored in the register, and selects and outputs any one of the two pieces of input data to the floating point multiply-adder according to an instruction type code indicating the type of a floating point instruction,

wherein when the instruction type code indicates a Taylor series multiply-add instruction, the selection and output section outputs the coefficient data to the floating point multiply-adder.

7. The processing apparatus according to claim 1, the processing apparatus further comprising a Taylor series multiply-add instruction comprising a field to set an instruction type code indicating a Taylor series multiply-add instruction, a field to set first information indicating a register for storing one operand value of a multiply operation of floating point multiply-add operation, a field to set second information indicating a register for storing the other operand value of the multiply operation of the floating point multiply-add operation, a field to set third information specifying a register to which the operation result of the floating point multiply-add operation should be outputted, a field to set fourth information specifying a register storing identification information of the coefficient table and a field to set fifth information specifying the degree of the Taylor series,

wherein data necessary for the floating point multiply-adder to execute a Taylor series operation is read from the register and the coefficient table set storage section through the register data reading section and the coefficient data reading section according to the decoding result of the Taylor series multiply-add instruction and the data is supplied to the floating point multiply-adder.

8. The processing apparatus according to claim 1, the processing apparatus further comprising a Taylor series multiply-add instruction comprising a field to set an instruction type code indicating a Taylor series multiply-add instruction, a field to set first information indicating a register storing one operand value of a multiply operation of floating point multiply-add operation, a field to set second information specifying a register storing the other operand value of multiply operation of multiply-add operation of the floating point multiply-add operation, a field to set third information specifying a register to which the operation result of the floating point multiply-add operation should be outputted and a field to set fourth information specifying the degree of Taylor series,

wherein some bits of the data of the register specified by the second information are used as information specifying identification information of the coefficient table, data necessary for the floating point multiply-adder to execute a Taylor series operation is read from the register and the coefficient table set storage section through the register data reading section and the coefficient data reading section according to the decoding result of the Taylor series multiply-add instruction and the data is supplied to the floating point multiply-adder.

9. The processing apparatus according to claim 1, the processing apparatus further comprising a Taylor series multiply-add instruction comprising a field to set an instruction type code indicating a Taylor series multiply-add instruction, a field to set first information indicating a register storing one operand value of a multiply operation of floating point multiply-add operation, a field to set second information specifying a register storing the other operand value of multiply operation of multiply-add operation of the floating point multiply-add operation, a field to set third information specifying a register to which the operation result of the floating point multiply-add operation should be outputted and a field to set fourth information specifying the degree of Taylor series,

wherein some bits of the data of the register specified by the first information are used as information specifying identification information of the coefficient table, data necessary for the floating point multiply-adder to execute a Taylor series operation is read from the register and the coefficient table set storage section through the register data reading section and the coefficient data reading section according to the decoding result of the Taylor series multiply-add instruction and the data is supplied to the floating point multiply-adder.

10. The processing apparatus according to claim 1, wherein the processing apparatus omits the field to set the first information specifying the number of the register storing one operand value of multiply operation of floating point multiply-add operation,

uses the field to set the third information specifying the register to which the operation result of the floating point multiply-add operation should be outputted as information specifying the register storing one operand value of multiply operation of the floating point multiply-add operation instead, and

reads data necessary for the floating point multiply-adder to execute a Taylor series operation from the register and the coefficient table set storage section through the register data reading section and the coefficient data reading section according to the decoding result of the Taylor series multiply-add instruction and supplies the data to the floating point multiply-adder.

11. The processing apparatus according to claim 7, wherein the processing apparatus omits the field to set the second information specifying the number of the register storing the other operand value of multiply operation of floating point multiply-add operation,

uses the field to set the third information specifying the register to which the operation result of the floating point multiply-add operation should be outputted as information specifying the register storing the other operand value of multiply operation of the floating point multiply-add operation instead, and

reads data necessary for the floating point multiply-adder to execute a Taylor series operation from the register and the coefficient table set storage section through the register data reading section and the coefficient data reading section according to the decoding result of the Taylor series multiply-add instruction and supplies the data to the floating point multiply-adder.

12. The processing apparatus according to claim 1, wherein the processing apparatus further specifies a setting position of coefficient data in the coefficient table set storage section using coefficient table specification information specifying the coefficient table and degree specification information specifying the degree of Taylor series.

13. The processing apparatus according to claim 12, the processing apparatus further comprising a coefficient table set update section that sets coefficient data at the setting position in the coefficient table set storage section.

14. The processing apparatus according to claim 13, the processing apparatus further comprising a coefficient table set update instruction comprising a field to set an instruction type code indicating data update of the coefficient table, a field to set first information specifying a register storing one operand value of multiply operation of multiply-add operation, a field to set second information specifying a register storing the other operand value of multiply operation of multiply-add operation, a field to set third information specifying a register storing identification information of the coefficient table, and a field to set fourth information specifying the degree information of Taylor series,

wherein the coefficient table set update section causes the floating point multiply-adder to execute a multiply operation of a first register value specified by the first information and a second register value specified by the second information according to the decoding result of the coefficient table set update instruction and writes the multiply operation result in a storage area of the coefficient data of the degree specified by the fourth information of the coefficient table specified by the value of the register specified by the third information.

15. A method of controlling a processing apparatus having a floating point multiply-adder, comprising:

storing operand data with a register;

reading the operand data stored in the register by a register data reading section;

storing a coefficient table storing coefficient data of a Taylor series operation by a coefficient table set storage section;

reading the coefficient data of the Taylor series using the degree information of the Taylor series and identification information of the coefficient table from the coefficient table set storage section by a coefficient data reading section; and

executing by a floating point multiply adder the Taylor series operation using the coefficient data read by the coefficient data reading section and data or bypass data read from the register.

16. The method of controlling a processing apparatus according to claim 15, wherein the coefficient table stores only coefficient data of even number degrees for a mathematical function which is an even function and only coefficient data of odd number degrees for a mathematical function which is an odd function.

17. The method of controlling a processing apparatus according to claim 16, wherein the odd function is a sine function and the even function is a cosine function, and

the coefficient table set storage section has a coefficient table of the sine function and a coefficient table of the cosine function.

18. The method of controlling a processing apparatus according to claim 17, wherein when performing the sine function or the cosine function using a Taylor series operation, the coefficient table of the sine function or the coefficient table of the cosine function is chosen to use depending on the range of input arguments of the mathematical functions.

19. The method of controlling a processing apparatus according to claim 18, wherein when the input argument of the sine function or the cosine function is outside a range of −

π

/4 to +π

/4, the input argument is converted so that the input argument of the sine function or the cosine function falls within the range of −

π

/4 to +π

/4 and a Taylor series operation is executed using the coefficient data of the coefficient table of the sine function or cosine function obtained by the input argument conversion.

20. The method of controlling a processing apparatus according to claim 15, wherein the processing apparatus further comprises a selection and output section that receives coefficient data in the coefficient table set storage section read by the coefficient data reading section and data or bypass data read by the register data reading section and stored in the register as input, and selects and outputs any one of the two pieces of input data to the floating point multiply-adder according to the instruction type code indicating the type of floating point instruction, and

the method of controlling a processing apparatus further comprises, when the instruction type code indicates a Taylor series multiply-add instruction, by the selection and output section of outputting the coefficient data to the floating point multiply-adder.