DESIGN STRUCTURE FOR DYNAMICALLY ALLOCATING LANES TO A PLURALITY OF PCI EXPRESS CONNECTORS

• US 20080228981A1
• Filed: 06/02/2008
• Published: 09/18/2008
• Est. Priority Date: 05/24/2006
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kern, Eric R., Baker, Marcus A., ATHERTON, William E.
• Granted Patent: US 8,103,993 B2
• Time in Patent Office: Days
• US Class Current: 710/300
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for dynamically allocating lanes to a plurality of PCI Express connectors is disclosed that include identifying whether a PCI Express device is installed into each PCI Express connector, and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector. Dynamically allocating lanes to a plurality of PCI Express connectors may also include identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors, creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors, and receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors.

Claims

1. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

an apparatus for dynamically allocating lanes to a plurality of PCI Express connectors, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of;

identifying whether a PCI Express device is installed into each PCI Express connector; and

assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector.

2. The design structure of claim 1, further comprising:

computer program instructions capable of identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors, wherein assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector further comprises assigning the lanes to each PCI Express connector in dependence upon the identified device types.

3. The design structure of claim 1, further comprising:

computer program instructions capable of creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors, wherein assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector further comprises assigning the lanes to each PCI Express connector in dependence upon the allocation rules.

4. The design structure of claim 1, further comprising:

computer program instructions capable of receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors, wherein assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector further comprises assigning the lanes to each PCI Express connector in dependence upon the user allocation preferences.

5. The design structure of claim 1, further comprising:

computer program instructions capable of identifying historic data traffic for each PCI Express device installed into the plurality of PCI Express connectors, wherein assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector further comprises assigning the lanes to each PCI Express connector in dependence upon the historic data traffic.

6. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the apparatus.

7. The design structure of claim 1, wherein the design structure resides on the machine readable storage medium as a data format used for the exchange of layout data of integrated circuits.