METHOD AND DEVICE FOR SECURING THE READING OF A MEMORY

• US 20080228989A1
• Filed: 12/12/2007
• Published: 09/18/2008
• Est. Priority Date: 12/18/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Berard, Nicolas, Bancel, Frederic, Hely, David
• Granted Patent: US 7,747,935 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A method reads a datum saved in a memory by selecting an address of the memory in which the datum to be read is saved, reading the datum in the memory at the selected address, saving the datum read in a storage space, and when the memory is not being accessed by a CPU, reading the datum in the memory, reading the datum saved in the storage space, and activating an error signal if the datum read in the memory is different from the datum saved. The method can be applied particularly to the protection of smart card integrated circuits.

Claims

1. A method, comprising:

selecting an address of a memory;

reading a datum at the selected address;

saving the datum read in a storage space;

reading the datum from the memory;

reading the datum saved in the storage space; and

activating an error signal if the datum read from the memory is different from the datum saved in the storage space.

2. The method according to claim 1, wherein the datum read is saved in the storage space in association with its address in the memory.

3. The method according to claim 1, wherein several data read at consecutive addresses in the memory are saved in the storage space in association with a single address and a number corresponding to the number of data saved in association with the address.

4. The method according to claim 1, further comprising:

reading data at addresses in the memory; and

saving the data in the storage space, wherein the data saved in the storage space are checked according to a random order.

5. The method according to claim 1, further comprising:

reading data at addresses in the memory; and

saving the data randomly in the storage space.

6. The method according to claim 1, comprising:

reading data at addresses in the memory;

saving the data in the storage space; and

interrupting the reading of the memory when the storage space is full, and checking whether the data saved in the storage space are identical to the corresponding data in the memory.

7. The method according to claim 6, wherein the interrupting step includes either blocking a clock signal pacing a central processing unit accessing the memory, or triggering the execution by the central processing unit of a waiting routine stored in another memory.

8. The method according to claim 1, wherein the reading the datum at the selected address is performed in response to a read request from a central processing unit and the reading the datum from the memory is performed while the central processing unit is not accessing the memory.

9. A device for protecting the reading of a memory, comprising:

a storage space configured to save a datum read in the memory, and an address of the memory in association with the datum saved;

means for reading the datum in the memory by using the address saved;

a comparator configured to compare the datum saved in the storage space with the datum read in the memory; and

means for activating an error signal if the datum saved is different from the datum read in the memory.

10. The device according to claim 9, wherein the storage space is configured to store data from the memory, and for each datum saved, the address of the datum in the memory.

11. The device according to claim 9, wherein the storage space is configured to store a single address for a set of saved data located at consecutive addresses in the memory, and a number corresponding to the number of data in the set of data.

12. The device according to claim 9, wherein the storage space is configured to store data from the memory, and wherein the data are saved in the storage space in a stack managed in FIFO or LIFO mode.

13. The device according to claim 9, wherein the storage space is configured to store data from the memory and addresses respectively corresponding to the data, wherein the addresses are saved in the storage space in a stack managed in FIFO or LIFO mode.

14. The device according to claim 9, wherein the memory to be protected is integrated with the storage space, means for reading, comparator, and means for activating.

15. An integrated circuit, comprising:

a central processing unit;

a memory read by the central processing unit;

a protection device that includes;

a storage space configured to save each datum read from the memory by the central processing unit;

means for checking, while the central processing unit is not accessing the memory, the data saved in the storage space, the checking including reading the data from the memory, comparing each datum saved in the storage space with a corresponding datum read from the memory, and activating an error signal if the datum saved is different from the datum read from the memory.

16. The integrated circuit according to claim 15, wherein the protection device comprises a multiplexer having a first input coupled to an address bus of the central processing unit, a second input coupled to the storage space, and an output coupled to an address bus of the memory, the multiplexer being structured to apply to the memory a read address coming either from the central processing unit, or from the storage space.

17. The integrated circuit according to claim 15, wherein the protection device comprises means for controlling the reading of the memory while the central processing unit is not accessing the memory.