FLASH MEMORY DEVICE AND MEMORY SYSTEM

• US 20080229000A1
• Filed: 05/14/2007
• Published: 09/18/2008
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Won-Tae
• Granted Patent: US 7,941,586 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory system comprises a flash memory, a processing unit, and a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit, wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers.

Claims

1. A memory system comprising:

a flash memory;

a processing unit; and

a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit,

wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers.

2. The memory system of claim 1, wherein the flash controller is further configured to notify the processing unit whether the copy-back program operation of the flash memory is ended.

3. The memory system of claim 1, wherein the flash controller is further configured to generate one or more commands, addresses, and data in hardware during the copy-back program operation.

4. The memory system of claim 1, wherein the flash controller is further configured to perform an error correcting and detecting operation with respect to data stored in the flash controller during the copy-back program operation.

5. The memory system of claim 4, wherein when no error is detected in the stored data, the flash controller outputs a destination address and a command to the flash memory according to information set in the address register.

6. The memory system of claim 4, wherein when an error is detected in the stored data, the flash controller outputs a destination address and a command to the flash memory together with error-corrected data according to information set in the address register.

7. The memory system of claim 1, wherein the flash controller is further configured to repeat a copy-back program operation of the flash memory based on information set in the control register.

8. The memory system of claim 1, wherein during the copy-back program operation, page data is copied back to a plane of the flash memory, source and destination addresses of the same plane being stored in the address register.

9. The memory system of claim 1, wherein during the copy-back program operation, page data is copied back in different planes of the flash memory at the same time, source and destination addresses of each plane being stored in the address register.

10. The memory system of claim 1, wherein during the copy-back program operation, page data is copied back from a first plane to a second plane of the flash memory.

11. The memory system of claim 1, wherein the control register is further configured to store control information including at least one of hardware copy-back program start information, interrupt enable information, interrupt status information, ECC auto correction information, copy-back repeat number information, source address increment/decrement information, destination address increment/decrement information, and plane selection information.

12. The memory system of claim 11, wherein the flash controller is further configured to control a copy-back program operation when the hardware copy-back program start information of the control register is set.

13. The memory system of claim 11, wherein the flash controller is configured to repeat a copy-back program operation based on at least one of the copy-back repeat number information, the source address increment/decrement information, and the destination address increment/decrement information.

14. The memory system of claim 1, further including a first RAM which temporarily stores data to be stored in the flash memory.

15. The memory system of claim 14, wherein the flash controller, the processing unit, and the first RAM are electrically connected to a system bus.

16. The memory system of claim 15, wherein the flash controller comprises:

a second RAM configured to temporarily store data read from the flash memory for the copy-back program operation;

an error detecting and correcting circuit configured to detect and correct an error with respect to the data read from the flash memory; and

a state machine configured to generate one or more commands and addresses for the copy-back program operation based on information stored in the address and control registers.

17. The memory system of claim 16, wherein the second RAM is electrically isolated from the system bus.

18. The memory system of claim 1, wherein the memory system includes a memory card.

19. A flash memory device comprising:

a memory cell array including a plurality of pages-a read/program circuit configured to perform read and program operations with respect to the memory cell array;

a repeat register configured to store repeat data; and

control logic which controls the read/program circuit so as to repeat a copy-back program operation according to the repeat data stored in the repeat register.

20. The flash memory device of claim 19, wherein the repeat data includes at least one of copy-back repeat number information, source address increment/decrement information, and destination address increment/decrement information.

21. The flash memory device of claim 20, wherein the repeat register is set with the repeat data input together with a repeat command before a read operation of a page is performed.

22. The flash memory device of claim 20, wherein the repeat register is set with the repeat data input together with a repeat command after a read operation of a page is performed and before a program operation is carried out with respect to a destination address.

23. The flash memory device of claim 20, wherein the repeat register includes non-volatile memory configured to store the repeat data.

24. The flash memory device of claim 19, wherein when a repeat command is input, the control logic controls the read/program circuit according to the repeat data in the repeat register so as to repeat a copy-back program operation.

25. The flash memory device of claim 24, wherein the repeat command is input before a read operation of a page is carried out.

26. The flash memory device of claim 24, wherein the repeat command is input after a read operation of a source page is performed and before a program operation is carried out with respect to a destination address.

27. The flash memory device of claim 24, wherein the repeat command includes a reference to a source address and a destination address.

28. The flash memory device of claim 19, wherein the repeat data is stored in the repeat register based on one or more commands, each command including a reference to a source address and destination address.

29. The flash memory device of claim 19, further comprising:

an error detecting block configured to detect an error during the copy-back program operation.

30. The flash memory device of claim 29, wherein when an error is detected during the copy-back program operation, the control logic terminates the copy-back program operation and outputs information related to the error detected.