Expanding memory support for a processor using virtualization

• US 20080229053A1
• Filed: 03/13/2007
• Published: 09/18/2008
• Est. Priority Date: 03/13/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Leija, Javier, Campini, Edoardo
• Application Number:
  US11/717,325
• Publication Number:
  US 20080229053A1
• Time in Patent Office: Days
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10

Abstract

In one embodiment, the present invention includes a system including a processor to access a maximum memory space of a first size using a memory address having a first length, a chipset coupled to the processor to interface the processor to a memory including a physical memory space, where the chipset is to access a maximum memory space larger than the first maximum memory space, and a virtual machine monitor (VMM) to enable the processor to access the full physical memory space of a memory. Other embodiments are described and claimed.

Claims

1. A system comprising:

a processor to execute instructions, the processor to access a maximum memory space of a first size using a memory address having a first length;

a chipset coupled to the processor to interface the processor to a memory including a physical memory space, wherein the chipset is to access a maximum memory space of a second size using a memory address of a second length, the second size and second length greater than the first size and the first length;

the memory coupled to the chipset having a physical memory space larger than the maximum memory space of the first size; and

a virtual machine monitor (VMM) to enable the processor to access the full physical memory space of the memory.

2. The system of claim 1, where the VMM is executed on the processor.

3. The system of claim 2, wherein the chipset includes an extended direct memory access (EDMA) controller to move blocks of data into and out of the maximum memory space of the first size from another portion of the memory responsive to the VMM.

4. The system of claim 3, wherein the VMM is to instruct the EDMA controller to move data from a portion of the memory addressed beyond the maximum memory space of the first size to a location in the memory of the maximum memory space of the first size.

5. The system of claim 1, wherein the processor includes a first core and second core, wherein the first core and the second core are to access separate blocks of the memory, wherein each of the separate blocks are greater than the maximum memory space of the first size.

6. The system of claim 5, wherein the VMM is to enable the first core to access a greater portion of the memory than the second core.

7. The system of claim 6, wherein the VMM includes a mapping table to map memory addresses of the maximum memory space of the first size to memory addresses in the physical memory space larger than the maximum memory of the first size.

8. The system of claim 7, wherein the VMM further comprises an allocator to dynamically allocate differing amount of the physical memory space to the first and second cores based at least in part on a priority level associated with the first and second cores.

9. A method comprising:

allocating a first portion of a physical memory to a first core of a processor and allocating a second portion of the physical memory to a second core of the processor, wherein the first portion and the second portion are each at least equal to a native memory address space of the processor;

receiving a memory request at a virtual machine monitor (VMM) from the first core; and

instructing a direct memory access (DMA) controller of an interface coupled between the processor and the physical memory to move a memory block including data of the memory request into a portion of the physical memory visible to the first core, the portion of the physical memory visible to the first core corresponding to the native address space of the processor.

10. The method of claim 9, further comprising performing the memory request.

11. The method of claim 9, further comprising determining a number of processing engines in the processor and dynamically allocating different portions of the physical memory to each of the processing engines.

12. The method of claim 11, further comprising re-allocating at least one of the previously allocated portions of the physical memory to a different one of the processing engines if a priority level changes.

13. The method of claim 9, further comprising executing an application on the first core in a native binary form, wherein a portion of the physical memory greater than the native address space of the processor is invisible to the application and the first core, yet accessible thereto via the VMM.

14. The method of claim 9, further comprising extending the memory addressability of the processor using the VMM and without further hardware.