Method of sharing registers in a processor and processor

• US 20080229062A1
• Filed: 03/12/2007
• Published: 09/18/2008
• Est. Priority Date: 03/12/2007
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Gregorio, Lorenzo Di
• Application Number:
  US11/716,990
• Publication Number:
  US 20080229062A1
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A method of sharing registers in a processor includes executing a data processing instruction so as to obtain a result of the data processing instruction, which is to be written into a register of the processor. Register sharing information is obtained so as to control writing of the result into the register and/or at least one further register of the processor.

Claims

1. A method of sharing registers in a processor, the method comprising:

executing a data processing instruction;

obtaining a result of the data processing instruction, the result to be written into a register of the processor; and

obtaining a register sharing information so as to control writing of the result into the register and/or at least one further register of the processor.

2. The method according to claim 1, further comprising:

forwarding the result of the data processing instruction between different processing stages of the processor.

3. The method according to claim 2, wherein said forwarding is accomplished taking into account said register sharing information.

4. The method according to claim 3, wherein said forwarding of the result includes an evaluation whether said register or said at least one further register are used in a processing stage.

5. The method according to claim 1, wherein said writing of said result into the register and/or the at least one further register is accomplished within one clock cycle.

6. The method according to claim 1, wherein said register and said at least one further register are associated with different contexts of a register file.

7. The method according to claim 1, wherein said register sharing information specifies whether said register is global with respect to said at least one further register.

8. The method according to claim 1, further comprising:

configuring said register sharing information to control the transfer of data between different instruction threads running on the processor.

9. The method according to claim 1, further comprising:

providing a table memory to hold said register sharing information.

10. The method according to claim 1, wherein said result of the data processing instruction does not depend on said register sharing information.

11. A processor, comprising:

a processing stage to execute data processing instructions;

a register file having a plurality of registers; and

a write control to control writing of a result of a data processing instruction into the register file, wherein the write control is supplied with register sharing information to control writing of said result into the register of the register file and/or at least one further register of the register file.

12. The processor according to claim 11, further comprising forwarding logic to forward said result of the data processing instruction from said processing stage to at least one further processing stage.

13. The processor according to claim 12, wherein the forwarding logic is controlled on the basis of said register sharing information.

14. The processor according to claim 12, wherein the forwarding logic comprises evaluation circuitry to evaluate whether said register and/or at least one further register into which said result is to be written according to the register sharing information are used in a further processing stage.

15. The processor according to claim 11, further comprising a table memory to hold said register sharing information.

16. The processor according to claim 15, wherein said table memory can be accessed in one write operation and at least one read operation within one clock cycle.

17. The processor according to claim 15, wherein the processor comprises a plurality of processor cores coupled to the table memory.

18. A computer system, comprising:

a processor to execute a program code, wherein said processor comprises;

a register file having a plurality of registers;

a processing stage to execute data processing instructions of the program code; and

a write control to control writing of a result of a data processing instruction into the register file, wherein the write control is supplied with register sharing information to control writing of said result into a register and/or at least one further register of the register file.

19. The computer system according to claim 18,

wherein said processor supports a plurality of threads of the program code;

and

wherein said register file comprises a corresponding set of registers for each of the threads.

20. The computer system according to claim 19, wherein said register sharing information defines whether a register of a thread is declared as global with respect to a corresponding register of at least one further thread.

21. A communication device, comprising:

a protocol processor to handle data packets, wherein said protocol processor comprises;

a register file having a plurality of registers;

a processing stage to execute data processing instructions; and

a write control to control writing of a result of a data processing instruction into the register file, wherein the write control is supplied with register sharing information to control writing of said result into a register of the register file and/or at least one further register of the register file.

22. The communication device according to claim 21, wherein said protocol processor is an embedded component of the communication device.