POWER MANAGING METHOD OF A SCHEDULING SYSTEM AND RELATED SCHEDULING SYSTEM

• US 20080229125A1
• Filed: 03/05/2008
• Published: 09/18/2008
• Est. Priority Date: 03/16/2007
• Status: Abandoned Application

• Current Assignee: Qisda Corporation
• Original Assignee: Qisda Corporation
• Inventors: Lee, Chang-Hung, Lin, Tson-Yee
• Application Number:
  US12/042,337
• Publication Number:
  US 20080229125A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A scheduling system includes a main processor, a micro control unit and a power supply. The main processor has a first memory module for storing a plurality of scheduled times. The micro control unit has a second memory module for storing a first scheduled time of the plurality of scheduled times provided by the first memory module and a timer for providing a real time. A corresponding power managing method includes: (a) starting the micro control unit; (b) the micro control unit determining whether the first scheduled time is stored in the second memory module according to a schedule flag; (c) the micro control unit determining a correlation between the first scheduled time and the real time; and (d) the micro control unit controlling the power supply to power on or power off the main processor of the scheduling system according to determined results in step (b) and step (c).

Claims

1. A power managing method of a scheduling system, the scheduling system comprising a main processor, a micro control unit and a power supply, the main processor having a first memory module for storing a plurality of scheduled times, the micro control unit having a second memory module for storing a first scheduled time of the plurality of scheduled times provided by the first memory module and a timer for providing a real time, the power managing method comprising:

(a) starting the micro control unit;

(b) the micro control unit determining whether the first scheduled time is stored in the second memory module according to a schedule flag;

(c) the micro control unit determining a correlation between the first scheduled time and the real time; and

(d) the micro control unit controlling the power supply to power on or power off the main processor of the scheduling system according to determined results in step (b) and step (c).

2. The power managing method of claim 1 further comprising determining whether the micro control unit has been reset according to a reset flag after starting the micro control unit.

3. The power managing method of claim 2 further comprising the micro control unit powering on the main processor to generate a message to inform a user of resetting the real time when the micro control unit has been reset.

4. The power managing method of claim 1, wherein the micro control unit determining whether the first scheduled time is stored in the second memory module according to the schedule flag comprises the micro control unit controlling the power supply to power off the main processor so as to make the scheduling system enter a standby mode when the schedule flag is equal to 0.

5. The power managing method of claim 1, wherein the micro control unit determining whether the first scheduled time is stored in the second memory module according to the schedule flag comprises the micro control unit determining the correlation between the first scheduled time and the real time when the scheduled flag is equal to 1.

6. The power managing method of claim 1, wherein the micro control unit determining the correlation between the first scheduled time and the real time comprises the micro control unit controlling the power supply to power off the main processor so as to make the scheduling system enter a standby mode when the first scheduled time is later than the real time.

7. The power managing method of claim 1, wherein the micro control unit determining the correlation between the first scheduled time and the real time comprises the micro control unit controlling the power supply to power on the main processor and storing a second scheduled time of the plurality of scheduled times provided by the first memory module into the second memory module when the first scheduled time is earlier than the real time, the second scheduled time being later than the real time.

8. The power managing method of claim 1, wherein the micro control unit determining the correlation between the first scheduled time and the real time comprises the micro control unit controlling the power supply to power on the main processor to perform a scheduled procedure corresponding to the first scheduled time when the first scheduled time conforms to the real time.

9. The power managing method of claim 8, wherein the scheduled procedure is a scheduled recording.

10. The power managing method of claim 8 further comprising the micro control unit controlling the power supply module to power off the main processor so as to make the scheduling system enter a standby mode after the scheduled procedure is finished.

11. The power managing method of claim 1, wherein the micro control unit further comprises an interior power source for providing the timer with power when the power supply is turned off.

12. A scheduling system comprising:

a main processor for performing a scheduled procedure, the main processor having a first memory module for storing a plurality of scheduled times;

a micro control unit electrically connected to the main processor for determining whether a first scheduled time is stored in the second memory module according to a schedule flag and whether the first scheduled time conforms to the real time so as to control the power supply to power on or power off the main processor, the micro control unit having a second memory module for storing the first scheduled time provided by the first memory module and a timer for providing the real time; and

a power supply electrically connected to the main processor and the micro control unit for providing the scheduling system with exterior power;

wherein the micro control unit controls the power supply to power on the main processor of the scheduling system to perform the scheduled procedure when the schedule flag is equal to 1 and the micro control unit determines the first scheduled time conforms to the real time.

13. The scheduling system of claim 12, wherein the micro control unit is used for determining whether the micro control unit has been reset according to a reset flag.

14. The scheduling system of claim 13 further comprising an input interface for inputting a time into the timer to reset the real time when the micro control unit has been reset.

15. The scheduling system of claim 12, wherein the micro control unit controls the power supply to power off the main processor so as to make the scheduling system enter a standby mode when the micro control unit determines the first scheduled time is later than the real time.

16. The scheduling system of claim 12, wherein the scheduling system is a record scheduling system and the scheduled procedure is a scheduled recording.

17. The scheduling system of claim 12, wherein the micro control unit controls the power supply to power on the main processor and the main processor stores a second scheduled time of the plurality of scheduled times into the second memory module of the micro control unit when the micro control unit determines the first scheduled time is stored in the second memory module and the first scheduled time is earlier than the real time, the second scheduled time being later than the real time.

18. The scheduling system of claim 17, wherein the micro control unit controls the power supply to power off the main processor so as to make the scheduling system enter a standby mode after the main processor stores the second scheduled time into the second memory module of the micro control unit.

19. The scheduling system of claim 12, wherein the micro control unit further comprises an interior power source for providing the timer with power when the power supply is turned off.

20. The scheduling system of claim 19, wherein the interior power source is a battery.