ERROR DETECTION IN A COMMUNICATIONS LINK

• US 20080229174A1
• Filed: 03/13/2007
• Published: 09/18/2008
• Est. Priority Date: 03/13/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Miranda, Paul C.
• Granted Patent: US 7,913,150 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H03M 13/091 Parallel or block-wise CRC computation

Abstract

An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.

Claims

1. An apparatus for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation comprising:

a select circuit configured to select between a first digital code and a second digital code, the selection being based, at least in part, on a selected mode of operation, the first digital code being based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with the first mode of operation, the second digital code being based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with the second mode of operation; and

a circuit configured to generate a next value of an error detection code, based, at least in part, on a third digital code and a selected one of the first and second digital codes,

wherein the third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and the third logical operation is consistent with the first and second modes of operation.

2. The apparatus, as recited in claim 1, further comprising:

a first circuit configured to generate the first digital code based, at least in part, on the first logical operation of the at least first plurality of data bits of the data stream corresponding to the plurality of communications paths; and

a second circuit configured to generate the second digital code based, at least in part, on the second logical operation of the at least second plurality of data bits of the data stream; and

a third circuit configured to generate the third digital code based, at least in part, on the third digital code being based, at least in part, on the third logical operation of at least the plurality of bits of the current value of the error detection code.

3. The apparatus, as recited in claim 1, further comprising:

a control circuit configured to reset the current value of the error detection code periodically after a predetermined number of bit-times in response to the first mode being selected and configured to reset the current value of the error detection code on a per-packet basis in response to the second mode being selected.

4. The apparatus, as recited in claim 1, further comprising:

a control circuit configured to insert an error detection code into the data stream after a first predetermined number of bit-times from an end of the data bits used to generate the error detection code, the insertion being based, at least in part, on the next value of the error detection code and the insertion being in response to selection of the first mode and the control circuit being configured to append the error detection code to a packet including the data bits used to generate the error detection code in response to selection of the second mode.

5. The apparatus, as recited in claim 1, wherein the second logical operation includes at least one term for effectuating padding of the data stream by a predetermined number of bits, thereby reducing effects of burst-type errors affecting a packet of data and the error detection code.

6. The apparatus, as recited in claim 1, wherein the first, second, and third digital codes have the same number of bits and the digital code is generated by a bitwise operation of the third digital code and the selected one of the first and second digital codes.

7. The apparatus, as recited in claim 1, wherein the first and second pluralities of data bits include data bits corresponding to respective ones of a plurality of bit-times.

8. The apparatus, as recited in claim 1, wherein the next digital code is a cyclic redundancy check (CRC) code related to the data code by a polynomial function.

9. The apparatus, as recited in claim 8, wherein the polynomial function is

x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+x+1.

10. The apparatus, as recited in claim 1, wherein the first logical operation includes at least one term exclusive to the first logical operation and the second logical operation includes at least one term exclusive to the second logical operation.

11. A method for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation comprising:

generating a next value of an error detection code, based, at least in part, on a selected one of a first digital code and a second digital code and based, at least in part, on a third digital code,

wherein the first digital code is based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with the first mode of operation,

wherein the second digital code is based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with the second mode of operation,

wherein the third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and consistent with the first and second modes of operation.

12. The method, as recited in claim 11, further comprising:

generating the first digital code based, at least in part, on the first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with a first mode of operation;

generating the second digital code based, at least in part, on the second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with a second mode of operation; and

generating the third digital code based, at least in part, on the third logical operation of the at least a plurality of bits of the current value of the error detection code and consistent with the first and second modes of operation.

13. The method, as recited in claim 11, further comprising:

resetting the current value of the error detection code periodically after a predetermined number of bit-times in response to the first mode being selected and configured to reset the current value of the error detection code on a per-packet basis in response to the second mode being selected.

14. The method, as recited in claim 11, further comprising:

inserting an error detection code based, at least in part, on the next value of the error detection code into the data stream after a first predetermined number of bit-times from an end of the data bits used to generate the error detection code, the insertion being in response to selection of the first mode; and

appending the next value of the error detection code to a packet including the data bits used to generate the next value of the error detection code in response to selection of the second mode.

15. The method, as recited in claim 11, further comprising:

selecting one of the first and second digital codes based, at least in part, on a selected mode of operation.

16. The method, as recited in claim 11, wherein the second logical operation includes at least one term for effectuating padding of the data stream by a predetermined number of bits, thereby reducing effects of burst-type errors affecting a packet of data and the error detection code.

17. The method, as recited in claim 11, wherein the first, second, and third digital codes have the same number of bits and the digital code is generated by a bitwise operation of one of the first and second digital codes with the third digital code.

18. The method, as recited in claim 11, wherein the first and second pluralities of data bits include data bits corresponding to respective ones of a plurality of bit-times.

19. The method, as recited in claim 11, wherein the next digital code is a cyclic redundancy check (CRC) code related to the data code by a polynomial function.

20. The method, as recited in claim 19, wherein the polynomial function is

x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+x+1.

21. The method, as recited in claim 11, wherein the first logical operation includes at least one term exclusive to the first logical operation and the second logical operation includes at least one term exclusive to the second logical operation.

22. An apparatus comprising:

means for selecting one of a first digital code and a second digital code, the first digital code being based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with a first mode of operation, the second digital code based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with a second mode of operation; and

means for generating a next value of an error detection code, based, at least in part, on a third digital code and a selected one of the first and second digital codes, the third digital code being based, at least in part, on third logical operation of at least a plurality of bits of a current value of the error detection code and consistent with the first and second modes of operation.

23. The apparatus, as recited in claim 22, further comprising:

means for resetting the current value of the error detection code periodically after a predetermined number of bit-times in response to the first mode being selected and configured to reset the current value of the error detection code on a per-packet basis in response to the second mode being selected.