ERROR DETECTION IN A COMMUNICATIONS LINK
First Claim
1. An apparatus for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation comprising:
- a select circuit configured to select between a first digital code and a second digital code, the selection being based, at least in part, on a selected mode of operation, the first digital code being based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with the first mode of operation, the second digital code being based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with the second mode of operation; and
a circuit configured to generate a next value of an error detection code, based, at least in part, on a third digital code and a selected one of the first and second digital codes,wherein the third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and the third logical operation is consistent with the first and second modes of operation.
1 Assignment
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Accused Products
Abstract
An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.
7 Citations
23 Claims
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1. An apparatus for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation comprising:
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a select circuit configured to select between a first digital code and a second digital code, the selection being based, at least in part, on a selected mode of operation, the first digital code being based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with the first mode of operation, the second digital code being based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with the second mode of operation; and a circuit configured to generate a next value of an error detection code, based, at least in part, on a third digital code and a selected one of the first and second digital codes, wherein the third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and the third logical operation is consistent with the first and second modes of operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for detecting errors in data transmitted over a communications link having at least a first mode of operation and a second mode of operation comprising:
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generating a next value of an error detection code, based, at least in part, on a selected one of a first digital code and a second digital code and based, at least in part, on a third digital code, wherein the first digital code is based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with the first mode of operation, wherein the second digital code is based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with the second mode of operation, wherein the third digital code is based, at least in part, on a third logical operation of at least a plurality of bits of a current value of the error detection code and consistent with the first and second modes of operation. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. An apparatus comprising:
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means for selecting one of a first digital code and a second digital code, the first digital code being based, at least in part, on a first logical operation of at least a first plurality of data bits of a data stream corresponding to a plurality of communications paths, the first logical operation being consistent with a first mode of operation, the second digital code based, at least in part, on a second logical operation of at least a second plurality of data bits of the data stream, the second logical operation being consistent with a second mode of operation; and means for generating a next value of an error detection code, based, at least in part, on a third digital code and a selected one of the first and second digital codes, the third digital code being based, at least in part, on third logical operation of at least a plurality of bits of a current value of the error detection code and consistent with the first and second modes of operation. - View Dependent Claims (23)
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Specification