METHOD FOR FAST ECC MEMORY TESTING BY SOFTWARE INCLUDING ECC CHECK BYTE

• US 20080229176A1
• Filed: 05/19/2008
• Published: 09/18/2008
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Vogt, Joerg-Stephan, Arnez, Andreas
• Granted Patent: US 8,145,961 B2
• Time in Patent Office: Days
• US Class Current: 714/768
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: H03M 13/096 Checksums

Abstract

The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Claims

1. A Random Access Memory Controller logic comprising a functional hardware component implementing a functional component for performing the steps of:

(a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving equation (1);

E*X=C  

 

(1)

wherein;

E is a known n×

m ECC matrix, where n is the number of data bits and m is the number of check bits,

X is a data pattern consisting of n bits fulfilling said equation (1), and

C is a check bit string consisting of m bits, wherein all bits have the logical value of “

1”

;

(b) generating a data pattern P3 by calculating a term (2) or (2′

);

(b1) P3=X XOR P1 or  

 

(2)

(b2) P3=X XOR P2  

 

(2′

)

wherein P1 and P2 are arbitrary data patterns of the same bit length as said X data pattern;

(c) writing said data pattern P3 into the data section of said memory unit, thus generating respective ECC data;

(d) testing said ECC memory section in an ECC test run by reading out the ECC data associated with said P3 data patterns;

(e) indicating an error, if said ECC procedure leads to an incorrect result.

2. The Random Access Memory Controller logic according to claim 6 applied with a dynamic memory.

3. A computer system comprising a functional hardware component implementing a functional component for performing the steps of:

(a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving an equation (1);

E*X=C  

 

(1)

wherein;

E is a known n×

m ECC matrix, where n is the number of data bits and m is the number of check bits,

X is a data pattern consisting of n bits fulfilling said equation (1), and

C is a check bit string consisting of m bits, wherein all bits have the logical value of “

1”

;

(b) generating a data pattern P3 by calculating a term (2) or (2′

);

(b1) P3=X XOR P1 or  

 

(2)

(b2) P3=X XOR P2  

 

(2′

)

wherein P1 and P2 are arbitrary data patterns of the same bit length as said X data pattern;

(c) writing said data pattern P3 into the data section of said memory unit, thus generating respective ECC data;

(d) testing said ECC memory section in an ECC test run by reading out the ECC data associated with said P3 data patterns;

(e) indicating an error, if said ECC procedure leads to an incorrect result.

4. A data processing system whose memory includes program code for performing respective steps of the method according to claim 1 when said computer program code portions are executed on said computer.

5. A computer program product stored on a computer usable medium comprising computer readable program means for causing a computer to perform the method of claim 1 when said computer program product is executed on said computer.