Processor instruction set

• US 20080229310A1
• Filed: 03/14/2007
• Published: 09/18/2008
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: XMOS Ltd.
• Original Assignee: XMOS Ltd.
• Inventors: May, Michael David
• Granted Patent: US 9,367,321 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence

Abstract

The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.

Claims

1. A processor comprising:

an execution unit; and

a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread;

wherein the execution unit is configured to execute thread scheduling instructions which manage said runnable statuses, the thread scheduling instructions including at least;

one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of said events upon which continued execution of the respective thread depends;

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.

2. A processor according to claim 1, wherein the thread scheduling instructions include a source event disable instruction which sets an event source to a mode in which it does not generate the event.

3. A processor according to claim 1 or claim 2, wherein the thread scheduling instructions include:

a thread event enable instruction which sets a control status of a thread to event-enabled to allow the enabled thread to accept events, and a thread event disable instruction which sets a control status of a thread to event-disabled to stop the disabled thread from accepting events.

4. A processor according to claim 1, wherein the execution unit is configured to execute one or more additional instructions each of which configures a parameter associated with an event source.

5. A processor according to claim 4, wherein the additional instructions include a set condition instruction which sets a condition upon which one of said event sources generates the respective event.

6. A processor according to claim 5, wherein the additional instructions include a set data instruction which provides data associated with the condition.

7. A processor according of claim 4, wherein the continuation point vector is one of said parameters associated with one of said event sources, and the additional instructions include at least a set vector instruction which sets said continuation point vector.

8. A processor according to claim 1, wherein the thread scheduling instructions further include an interrupt enable instruction which sets a control status of a thread to interrupt-enabled to allow the enabled thread to accept interrupts, and an interrupt disable instruction which sets a control status of a thread to interrupt-disabled to stop the disabled thread from accepting interrupts.

9. A processor according to claim 1, wherein the thread scheduling instructions further include:

an input instruction which pauses a thread pending input of data from an event source, and an output instruction which pauses a thread pending the availability of an event source for outputting data;

wherein continued execution of a thread paused by said input and output instructions does not involve retrieval of a continuation point vector for that thread.

10. A processor according to claim 1, wherein the thread scheduling instructions include a clear instruction to disable all events for a thread.

11. A processor according to claim 3, comprising at least one first register for storing said control statuses.

12. A processor according to claim 4, comprising at least one second register for storing said parameters.

13. A processor according to claim 1, comprising an interconnect system for establishing at least one channel between at least two third registers each arranged to store information relating to respective thread, at least one channel being an event source.

14. A processor according to claim 1, comprising at least one port being an event source.

15. A processor according to claim 1, wherein the execution unit is adapted to execute a plurality of said event source enable instructions each of which sets a respective event source to a mode in which it generates an event dependent on activity occurring at that source, and said wait instruction sets said one of the runnable statuses to suspended pending an event from any of said event-enabled sources.

16. A processor according to claim 9, wherein the processor is arranged to execute a first one of said event source enable instructions to enable a first event source to generate a first event dependent on a first activity occurring at the first source, to execute at least one of said additional instructions to configure one or more of said parameters for the first event source, to execute said wait instruction to suspend the respective thread pending the first activity, to disable the first source from generating the first event after occurrence of the first activity, to leave said parameters configured for the first event source after said disabling of the first source, and to re-use said parameters by executing a second of said event source enable instructions to enable the first source to generate a further instance of the first event dependent on a further occurrence of the first activity at the first source.

17. A processor according to claim 16, wherein the processor is arranged to execute at least one of said input and output instructions between said execution of said wait instruction and said execution of said second event source enable instruction.

18. A processor according to claim 1, wherein said wait instruction can be either a wait enable true instruction which waits only if its condition operand is true, or a wait enable false instruction which waits only if its condition operand is false.

19. A processor according to claim 1, wherein said event source enable instruction can be either a source event enable true instruction which enables the source to generate events if an operand is true and disables it otherwise, or an source event enable event enable false instruction which enables a source to generate events if an operand is false and disabled it otherwise.

20. A processor according to claim 1, wherein the execution unit is arranged to execute one of said thread event enable instruction and subsequently execute a plurality of said source event enable instructions each for a respective source.

21. A processor according to claim 1, wherein the processor is adapted to automatically disable a thread from accepting events upon occurrence of the respective event without executing a thread event disable instruction.

22. A processor according to claim 1, wherein the processor is adapted to automatically disable the event source from generating events upon occurrence of a respective event without executing a source event disable instruction.

23. A processor according to claim 1, wherein the processor is adapted to complete at least one wait, input or output instruction immediately if the respective event, data or availability is ready on or before execution of the respective instruction.

24. A method of controlling a thread scheduler to schedule threads for execution by an execution unit within a processor, the method comprising:

scheduling a plurality of threads in dependence on a respective status for each thread; and

operating the execution unit to execute thread scheduling instructions for managing statuses of threads, said thread scheduling instructions including at least;

one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of said events upon which continued execution of the respective thread depends

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.

25. A method according to claim 24, wherein the thread scheduling instructions include a source event disable instruction which sets the event source to a mode in which it does not generate events.

26. A method according to claim 24 or claim 25, wherein the thread scheduling instructions include:

a thread event enable instruction which sets a control status for a thread to event-enabled to allow the enabled thread to accept events, and a thread event disable instruction which sets a control status of a thread to event-disabled to stop the disabled thread from accepting events.

27. A method according to claim 24, further comprising executing one or more additional instructions each of which configures a parameter associated with an event source.

28. A method according to claim 27, wherein said additional instructions include a set condition instruction which sets a condition upon which one of said event sources generates the respective event.

29. A method according to claim 28, wherein said additional instructions include a set data instruction which provides data associated with the condition.

30. A method according to claim 27, wherein said continuation point vector is one of the parameters associated with one of said event sources, and said additional instructions include at least a set vector instruction which sets said continuation point vector.

31. A method according to claim 24, wherein the thread scheduling instructions further include:

an interrupt enable instruction which sets a control status for a thread to interrupt-enabled to allow the enabled thread to accept interrupts, and an interrupt disable instruction which sets a control status for a thread to interrupt-disabled to stop the disabled thread from accepting interrupts.

32. A method according to claim 24, wherein the thread scheduling instructions further include:

an input instruction which pauses a thread pending input of data from an event source, and an output instruction which pauses a thread pending the availability of an event source for outputting data;

wherein continued execution of a thread paused by said input and output instructions does not involve retrieval of a continuation point vector for that thread.

33. A method according to claim 24, wherein said thread scheduling instructions include a clear instruction to disable all events for a thread.

34. A method according to claim 26, comprising storing said control statuses in at least one first register.

35. A method according to claim 27, comprising storing said parameters in at least one second register.

36. A method according to claim 24, wherein the processor comprises an interconnect system providing at least one channel between at least two of said first registers, and the method comprises operating at least one channel as one of said event sources by indicating an event based on activity occurring over that channel.

37. A method according to claim 24, wherein the processor comprises at least one port, and the method comprises operating at least one port as one of said event sources by indicating an event based on activity occurring at that port.

38. A method according to claim 24, comprising:

executing a plurality of said event source enable instructions to set each of a plurality of respective event source to a mode in which it generates an event dependent on activity occurring at that source, and

executing said wait instruction to set said one of the runnable statuses to suspended pending an event from any of said event-enabled sources.

39. A method according to claim 32, comprising:

executing a first one of said event source enable instructions to enable a first event source to generate a first event dependent on a first activity occurring at the first source,

executing at least one of said additional instructions to configure one or more of said parameters for the first event source,

executing said wait instruction to suspend the respective thread pending the first activity,

disabling the first source from generating the first event after occurrence of the first activity,

leaving said parameters configured for the first event source after said disabling of the first source, and

re-using said parameters by executing a second of said event source enable instructions to enable the first source to generate a further instance of the first event dependent on a further occurrence of the first activity at the first source.

40. A method according to claim 39, comprising executing at least one of said input and output instructions between said execution of said wait instruction and said execution of said second event source enable instruction.

41. A method according to claim 24, wherein said wait instruction can be either a wait enable true instruction which waits only if its condition operand is true, or a wait enable false instruction which waits only if its condition operand is false.

42. A processor according to claim 24, wherein said event source enable instruction can be either a source event enable true instruction which enables the source to generate events if an operand is true and disables it otherwise, or an source event enable event enable false instruction which enables a source to generate events if an operand is false and disabled it otherwise.

43. A processor according to claim 24, wherein the execution unit is arranged to execute one of said thread event enable instruction and subsequently execute a plurality of said source event enable instructions each for a respective source.

44. A method according to claim 24, comprising automatically disabling a thread from accepting events upon occurrence of the respective event without executing a thread event disable instruction.

45. A method according to claim 24, comprising automatically disabling the event source from generating events upon occurrence of a respective event without executing a source event disable instruction.

46. A processor according to claim 24, comprising completing at least one wait, input or output instruction immediately if the respective event, data or availability is ready on or before execution of the respective instruction.

47. An execution unit configured to execute thread scheduling instructions which manage statuses of threads, the thread scheduling instructions including at least:

one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source; and

a wait instruction which sets one of said runnable statuses to suspended pending one of said events upon which continued execution of the respective thread depends,

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.

48. A method of scheduling a plurality of threads for execution by an execution unit, the method comprising:

executing thread scheduling instructions for managing statuses of threads, said thread scheduling instructions including at least;

one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source; and

a wait instruction which sets one of said runnable statuses to suspended pending one of said events upon which continued execution of the respective thread depends,

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.

49. A processor comprising:

execution means for executing thread scheduling instructions; and

thread scheduling means for scheduling a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread;

wherein the execution means is configured to execute said thread scheduling instructions to manage said runnable statuses, the thread scheduling instructions including at least;

one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of said events upon which continued execution of the respective thread depends;

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.

50. An execution unit configured to execute thread scheduling instructions which manage statuses of threads, the execution unit comprising means for executing a source event enable instruction which sets an event source to a mode in which it generates an event dependent on activity occurring at that source;

and

means for executing a wait instruction which sets one of said runnable statuses to suspended pending one of said events upon which continued execution of the respective thread depends,

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.

51. A computer program product comprising program code means for executing thread scheduling instructions for managing statuses of threads, said program code means comprising a first code portion for executing a source event enable instruction which sets an event source to a mode in which it generates an event dependent on activity occurring at that source;

and

a second code portion for executing a wait instruction which sets one of said runable statuses to suspended pending one of said events upon which continued execution of the respective thread depends,

wherein said continued execution comprises retrieval of a continuation point vector for the respective thread.