QUALITY OF SERVICE SCHEDULING FOR SIMULTANEOUS MULTI-THREADED PROCESSORS

• US 20080229321A1
• Filed: 05/30/2008
• Published: 09/18/2008
• Est. Priority Date: 07/19/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tremaine, Robert B., Wisniewski, Robert W., Krieger, Orran Y., Rosenburg, Bryan S.
• Granted Patent: US 8,869,153 B2
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 2209/5019 Workload prediction
• CPC Class Codes: G06F 2209/508 Monitor
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/505 considering the load

Abstract

A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.

Claims

1. A method of providing quality of service scheduling in multithreaded processing, comprising:

identifying one or more hardware resources utilized by a thread in simultaneous multithreaded processing;

communicating the identified one or more hardware resource utilization; and

allowing reservation of the one or more hardware resources utilized by a thread in the simultaneous multithreaded processing.

2. The method of claim 1, wherein the step of identifying includes identifying one or more hardware resources utilized by a set of threads in simultaneous multithreaded processing.

3. The method of claim 1, wherein the step of identifying is performed by hardware.

4. The method of claim 1, wherein the step of communicating includes storing information pertaining to the identified one or more hardware resource utilization.

5. The method of claim 1, wherein the one or more hardware resources include one or more processing elements, functional units or cache memory or combination thereof.

6. The method of claim 1, wherein the one or more hardware resources includes at least a floating point unit, an integer unit, an arithmetic logic unit, a shifter, a register, a load-store unit, cache memory or combination thereof.

7. The method of claim 1, further including:

scheduling one or more threads based on information associated with the identified one or more hardware resource utilization.

8. The method of claim 7, wherein the step of scheduling is performed by an operating system.

9. The method of claim 1, further including:

reserving one or more hardware resources for a thread based on information associated with the identified one or more hardware resource utilization.

10. The method of claim 9, wherein the step of reserving is performed by an operating system.

11. The method of claim 9, wherein the step of reserving includes storing one or more data bits in a register accessible by hardware, the data bits identifying which one or more hardware resources to reserve for a thread.

12. The method of claim 1, wherein the step of communicating includes storing in a register accessible by an operating system, one or more data bits that identify one or more hardware resource utilization by a thread.

13. The method of claim 12, wherein the step of storing is performed by hardware.

14. The method of claim 1, further including:

analyzing information associated with the identified one or more hardware resource utilization by a thread.

15. The method of claim 1, further including:

communicating between software and hardware information associated with one or more threads by using software thread identifier to hardware thread identifier mapping.

16. The method of claim 1, further including:

restricting one or more hardware resources from a thread based on information associated with the identified one or more hardware resource utilization.

17. A method of providing quality of service scheduling in multithreaded processing, comprising:

accessing information associated with hardware resource utilization per thread in simultaneous multithreaded processing; and

scheduling one or more threads based on the information.

18. The method of claim 17, further including:

analyzing the information to determine at least one of memory utilization pattern, thread affinity concern, thread interference issue, and other thread resource behavior affecting utilization, and the step of scheduling includes scheduling one or more threads based on at least one of memory utilization pattern, thread affinity concern, thread interference issue, and other thread resource utilization affection behavior.

19. A method of providing quality of service scheduling in multithreaded processing, comprising:

accessing information associated with a thread'"'"'s use of one or more hardware resources on a core in simultaneous multithreaded processing; and

reserving one or more hardware resources based on the accessed information.

20. A system for providing quality of service scheduling in multithreaded processing, comprising:

a hardware controller on a processor operable to track a thread'"'"'s use of one or more hardware resources in simultaneous multithreaded processing, the hardware controller further operable to communicate information associated with the use of one or more hardware resources per thread; and

an operating system operable to access the information and schedule one or more threads based on the information.