SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT

• US 20080230833A1
• Filed: 03/23/2007
• Published: 09/25/2008
• Est. Priority Date: 03/23/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Zundel, Markus, Siemieniec, Ralf
• Granted Patent: US 7,615,847 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component having a semiconductor body having first and second semiconductor regions of a first conduction type, and a third semiconductor region of a second conduction type, which is complementary to the first conduction type. The second semiconductor region is arranged between the first and third semiconductor region and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region. In the second semiconductor region the dopant concentration is lower than the dopant concentration in the first semiconductor region. The dopant concentration in the second semiconductor region along a straight connecting line between the first and third semiconductor regions is inhomogeneous and has at least one minimum between the first and second junction regions, wherein the minimum is at a distance from the first and second junction regions.

Claims

1. A semiconductor component comprising:

a semiconductor body comprising;

at least one first semiconductor region of a first conduction type;

at least one second semiconductor region of the first conduction type; and

at least one third semiconductor region of a second conduction type, which is complementary to the first conduction type,

wherein

the second semiconductor region is arranged between the first and third semiconductor region and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region,

in the second semiconductor region the dopant concentration is lower than the dopant concentration in the first semiconductor region, and

the dopant concentration in the second semiconductor region along a straight connecting line between the first and third semiconductor regions is inhomogeneous and has at least one minimum between the first and second junction regions, wherein the minimum is at a distance from the first and second junction regions.

3. The semiconductor component as claimed in claim 1, wherein the minimum is arranged in that half of the second semiconductor region between the first and third semiconductor regions which faces the third semiconductor region.

5. The semiconductor component as claimed in claim 1, wherein the dopant concentration of the second semiconductor region decreases substantially monotonically proceeding from the first junction region as far as the minimum and increases substantially monotonically from the minimum as far as the second junction region.

6. The semiconductor component as claimed in claim 1, wherein the semiconductor body extends laterally, and the first, second and third semiconductor regions in the semiconductor body are arranged one above the other with regard to the lateral extent of the semiconductor body.

7. The semiconductor component as claimed in claim 6, wherein the semiconductor body has a first laterally extending surface and at least two trench structures which run substantially perpendicular to the first surface and extend from the first surface through the third semiconductor region at least as far as into the second semiconductor region, with the result that a mesa structure is formed between the trench structures.

8. The semiconductor component as claimed in claim 6, wherein the semiconductor body has a first laterally extending surface and at least two trench structures which run substantially perpendicular to the first surface and extend from the first surface through the third semiconductor region at least as far as into the first semiconductor region, with the result that a mesa structure is formed between the trench structures.

9. The semiconductor component as claimed in claim 7, wherein the connecting line runs through the mesa structure outside the trench structures.

10. The semiconductor component as claimed in claim 7, wherein the minimum is arranged in the mesa structure between the trench structures.

11. The semiconductor component as claimed in claim 7, wherein each trench structure has a width D_trench and the mesa structure has a width W_mesa along an imaginary common straight line, where W_mesa<

1.5*D_trench.

12. The semiconductor component as claimed in claim 7, wherein the minimum is arranged in the mesa structure above the bottom of the trench structures.

13. The semiconductor component as claimed in claim 7, wherein at least one electrode structure is in each case arranged in the trench structures, said at least one electrode structure being insulated from the semiconductor body by at least one dielectric layer.

14. The semiconductor component as claimed in claim 1, wherein a fourth semiconductor region of the first conduction type is arranged in the semiconductor body, wherein the fourth semiconductor region is embedded in the third semiconductor region and is spaced apart from the second semiconductor region.

15. The semiconductor component as claimed in claim 1, wherein the dopant concentration of the first conduction type in the second semiconductor region in the vicinity of the second junction region or at the second junction region is greater than 2*10¹⁶ cm⁻

3.

16. The semiconductor component as claimed in claim 1, wherein the dopant concentration of the first conduction type in the second semiconductor region in the vicinity of the second junction region or at the second junction region is greater than 5*10¹⁶ cm⁻

3.

17. The semiconductor component as claimed in claim 1, wherein the dopant concentration of the first conduction type in the second semiconductor region in the vicinity of the first junction region or at the first junction region is greater than 1*10¹⁷ cm⁻

3.

18. The semiconductor component as claimed in claim 1, wherein the dopant concentration of the first conduction type at the minimum lies approximately between 7*10¹⁵ cm⁻

3 and 1*10¹⁷ cm<sup>−

3</sup>.

2. A semiconductor component comprising:

a semiconductor body comprising;

at least one first semiconductor region of a first conduction type;

at least one second semiconductor region of the first conduction type; and

at least one third semiconductor region of a second conduction type, which is complementary to the first conduction type,

wherein

the second semiconductor region is arranged between the first and third semiconductor regions and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region,

in the second semiconductor region the dopant concentration is lower than the dopant concentration in the first semiconductor region, and

the second semiconductor region has a compensation doping of the second conduction type with at least one maximum between the first and second junction regions, wherein the compensation doping has at the maximum a dopant concentration which is lower than the dopant concentration of the first conduction type in the second semiconductor region.

4. The semiconductor component as claimed in claim 2, wherein the maximum is arranged in that half of the second semiconductor region between the first and third semiconductor regions which faces the third semiconductor region.

19. A power component with an at least partly vertical current flow, comprising:

a semiconductor body comprising;

a first surface;

a body region in the region of the first surface;

a drain zone located below the body region;

a drift zone located between the body region and the drain zone, wherein the drift zone together with the body region forms a pn junction, and together with the drain zone forms an nn⁺ or pp⁺ junction; and

at least two trench structures, which extend from the first surface at least as far as the drift zone, so that a mesa structure is formed between the trench structures,

wherein the doping profile of the majority charge carrier impurities in the drift zone has at least one minimum between the trench structures and between the pn junction and the nn⁺ or pp⁺ junction, wherein the minimum is in each case at a distance from the pn junction and the nn⁺ or pp⁺ junction, and/or

wherein the drift zone has a compensation doping of minority charge carrier impurities with at least one maximum between pn junction and nn⁺ or pp⁺ junction.

20. The power component as claimed in claim 19, wherein the dopant concentration of the majority charge carrier impurities in the drift zone in the vicinity of the pn junction or at the pn junction is greater than 2*10¹⁶ cm⁻

3.

21. The power component as claimed in claim 19, wherein the dopant concentration of the majority charge carrier impurities in the drift zone in the vicinity of the pn junction or at the pn junction is greater than 5*10¹⁶ cm⁻

3.

22. The power component as claimed in claim 19, wherein each trench structure has a width D_trench and the mesa structure has a width W_mesa along an imaginary common straight line, where W_mesa<

1.5*D_trench.

23. The power component as claimed in claim 19, wherein the trench structures extend vertically over more than half of the vertical extent of the drift zone.

24. The power component as claimed in claim 19, wherein the trench structures extend vertically into the drain zone.

25. The power component as claimed claim 19, wherein the trench structures are formed such that the distance d₁ between the bottom of the trench structures and the drain zone is less than or equal to the total width W_mesa of the mesa structure.

26. The power component as claimed claim 19, wherein the trench structures are formed such that the distance d₁ between the bottom of the trench structures and the drain zone is less than or equal to half the width of the mesa structure.

27. The power component as claimed in claim 19, wherein electrode structures are arranged in the trench structures, and the electrode structures are insulated from the semiconductor body by in each case at least one dielectric layer.

28. The power component as claimed in claim 27, wherein the dielectric layer has a smaller thickness in the region of the body region than in the region of the drift zone.

29. The power component as claimed in claim 27, wherein the dielectric layer, in the region of the drift zone, has a thickness d_{field oxide} and W_mesa<

3*d_{field oxide}.

30. The power component as claimed in claim 19, wherein a source zone is embedded into the body region.

31. A power component, comprising:

a silicon semiconductor body comprising;

a body region;

a drain zone; and

a drift zone, which is arranged between the body region and the drain zone, and together with the body region forms a pn junction,

wherein the drift zone has a dopant concentration n in the region of the pn junction or at the pn junction, which dopant concentration satisfies the following inequality

n>

1.13*10¹⁷ cm<sup>−

3</sup>*exp(−

V_br/85 V)

where V_br is the breakdown voltage.

32. The power component as claimed in claim 31, wherein the dopant concentration in the drift zone has a minimum, or wherein the drift zone has a compensation doping of minority charge carrier impurities with a maximum.

33. The power component as claimed in claim 31, wherein the dopant concentration n is defined by the inequality in the range of 10 V≦

V_br<

200 V.

34. The power component as claimed in claim 31, wherein the dopant concentration n is defined by the inequality in the range of 20 V≦

V_br≦

150 V.

35. A method for producing a semiconductor component comprising:

forming a first semiconductor region of a first conduction type;

forming a second semiconductor region of the first conduction type, wherein the second semiconductor region has a lower dopant concentration than the first semiconductor region;

forming a third semiconductor region of a second conduction type, which is complementary to the first conduction type,

wherein the semiconductor regions are formed such that

the second semiconductor region is arranged between the first and the third semiconductor regions, and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region, and

the second semiconductor region has an inhomogeneous dopant profile along a straight connecting line between the first and third semiconductor regions, with at least one minimum between the first and second junction region, wherein the minimum is at a distance from the first and second junction region.

36. The method as claimed in claim 35, further comprising:

providing a substrate having the first semiconductor region;

depositing a semiconductor layer of the first conduction type onto the first semiconductor region by means of epitaxy, wherein the semiconductor layer has an inhomogeneous dopant distribution with a minimum in the growth direction; and

forming the third semiconductor region spaced apart from the first semiconductor region in the upper region of the semiconductor layer with formation of the second junction region.

37. The method as claimed in claim 36, wherein during the deposition of the semiconductor layer at least one dopant is supplied and the concentration of the supplied dopant is varied in such a way as to form the inhomogeneous dopant distribution with the minimum.

38. The method as claimed in claim 37, wherein

the concentration of the supplied dopant during the deposition of the semiconductor layer decreases down to a minimum value during a first time segment,

is then kept largely constant at the minimum value during a second time segment, and

is subsequently set to at least a largely constant value, which is higher than the minimum value, during a third time segment.

39. The method as claimed in claim 37, wherein

the concentration of the supplied dopant during the deposition of the semiconductor layer decreases down to a minimum value during a first time segment,

is then kept largely constant at the minimum value or reduced further during a second time segment, and

after the completion of the semiconductor layer at least one dopant of the first conduction type is implanted into the semiconductor layer.

40. The method as claimed in claim 39, wherein the implantation of the dopant of the first conduction type is carried out such that the maximum of the implantation lies substantially below the third semiconductor region.

41. The method as claimed in claim 37, wherein during the deposition of the semiconductor layer the concentration of the supplied dopant is reduced only during a first time segment or during the entire deposition, and wherein afterward, by oxidation of uncovered surface regions of the semiconductor layer, dopant from the oxidized surface regions is segregated into non-oxidized regions in order to form the minimum.

42. The method as claimed in claim 37, wherein during the deposition of the semiconductor layer the concentration of the supplied dopant is reduced only during a first time segment or during the entire deposition, and wherein afterward, by oxidation of uncovered surface regions of the semiconductor layer, dopant from the oxidized surface regions is segregated into the region of the second junction region to be formed, in order to form the minimum.

43. The method as claimed in claim 41, wherein

the third semiconductor region is formed by implantation and indiffusion or by thermal activation of the dopant,

trench structures are produced in the semiconductor layer wherein the trench structures completely penetrate through the third semiconductor region that has been formed or is subsequently to be formed, and extend deeper than the third semiconductor region, wherein mesa structures remain between the trench structures, and

uncovered surfaces of the trench structures and the semiconductor layer or semiconducting regions are oxidized.

44. The method as claimed in claim 37, wherein the decrease in the dopant concentration during the deposition of the semiconductor layer is set such that, in the semiconductor layer, the dopant concentration decreases from approximately 2*10¹⁷ cm⁻

3 at the first junction region to a value of between approximately 7*10¹⁵ cm<sup>−

3</sup> and approximately 1*10¹⁷ cm<sup>−

3</sup> at the minimum.

45. The method as claimed in claim 36, wherein the dopant concentration is varied in a stepwise fashion.

46. The method as claimed in claim 35, further comprising:

providing a semiconductor body of the first conduction type;

forming the third semiconductor region in that region of the semiconductor body which is near the top side, with formation of the second junction region with respect to the semiconductor body;

thinning the semiconductor body at the rear side thereof;

forming the first semiconductor region in that region of the semiconductor body which is near the rear side, so that the first semiconductor region has a higher dopant concentration than the semiconductor body; and

forming the inhomogeneous dopant profile of the first conduction type with a minimum in the semiconductor body between the first junction region and the second junction region by implantation.

47. The method as claimed in claim 46, wherein a rise in the dopant concentration of the first conduction type in the semiconductor body in the direction of the second junction region is formed by implantation into the top side of the semiconductor body prior to the thinning of the semiconductor body.

48. The method as claimed in claim 46, wherein a rise in the dopant concentration of the first conduction type in the semiconductor body in the direction of the first junction region is formed by implantation into the rear side of the semiconductor body after the thinning of the semiconductor body.

49. The method as claimed in claim 46, wherein a dopant of the first conduction type or protons are implanted for the purpose of forming the rise.

50. The method as claimed in claim 48, wherein a dopant of the first conduction type or protons are implanted for the purpose of forming the rise.

51. A method for producing a semiconductor component comprising the steps:

forming a first semiconductor region of a first conduction type;

forming a second semiconductor region of the first conduction type, wherein the second semiconductor region has a lower dopant concentration than the first semiconductor region;

forming a third semiconductor region of a second conduction type, which is complementary to the first conduction type;

wherein the semiconductor regions are formed such that

the second semiconductor region is arranged between the first and the third semiconductor regions, and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region, and

the second semiconductor region has a compensation doping of the second conduction type with at least one maximum between the first and second junction regions, wherein the compensation doping at the maximum has a dopant concentration lower than the dopant concentration of the first conduction type in the second semiconductor region.

52. The method as claimed in claim 51, further comprising:

providing a substrate with the first semiconductor region;

depositing a semiconductor layer of the first conduction type onto the first semiconductor region by means of epitaxy; and

forming the third semiconductor region spaced apart from the first semiconductor region in the upper region of the semiconductor layer in order to form the second junction region,

wherein the compensation doping of the second conduction type is formed in the semiconductor layer between the third semiconductor region and the first semiconductor region.

53. The method as claimed in claim 52, wherein the compensation doping is introduced by supplying a dopant of the second conduction type during the deposition of the semiconductor layer.

54. The method as claimed in claim 52, wherein the compensation doping is introduced by means of a high-energy implantation of a dopant of the second conduction type into the semiconductor layer.

55. The method as claimed in claim 51, wherein the trench structures with electrode structures, which are insulated from the semiconductor layer and the semiconductor regions, are produced in the semiconductor layer.