RADIATION-HARDENED SILICON-ON-INSULATOR CMOS DEVICE, AND METHOD OF MAKING THE SAME
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Abstract
A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.
17 Citations
32 Claims
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1-18. -18. (canceled)
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19. A method of radiation hardening an ultrathin silicon on sapphire P-channel transistor including the act of:
implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A radiation hardened ultrathin silicon on sapphire P-channel transistor product produced by a process comprising the steps of:
implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface. - View Dependent Claims (27, 28, 29, 30, 31, 32)
Specification