SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING

• US 20080230873A1
• Filed: 03/22/2007
• Published: 09/25/2008
• Est. Priority Date: 03/22/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Higman, Jack M., Demircan, Ertugrul
• Granted Patent: US 7,820,520 B2
• Time in Patent Office: Days
• US Class Current: 257/620
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.

Claims

1. A method comprising:

providing an integrated circuit having a plurality of terminals for making electrical connection to the integrated circuit;

providing at least one device adjacent an outer edge of the integrated circuit, the at least one device comprising at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation; and

coupling the at least one device to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use.

2. The method of claim 1 further comprising:

forming the at least one device as a capacitor that couples capacitance to the one or more functional circuits during a non-test operation of the integrated circuit.

3. The method of claim 1 further comprising:

forming the at least one device as an inductor that couples inductance to the one or more functional circuits during a non-testing operation of the integrated circuit.

4. The method of claim 3 further comprising:

forming the inductor with a continuous metal conductor having a first end electrically connected to a first terminal of a predetermined one of the one or more functional circuits and a second end electrically connected to a second terminal of the predetermined one of the one or more functional circuits, the inductor looping between the outer edge and the plurality of terminals at least around the integrated circuit once.

5. The method of claim 1 further comprising:

forming the at least one device as a plurality of capacitors that each couples capacitance to any of the one or more functional circuits during non-testing operation of the integrated circuit.

6. The method of claim 1 wherein providing at least one device further comprises:

forming a plurality of capacitors comprising a common first electrode, the common first electrode comprising a continuous outer metal conductor around the outer edge of the integrated circuit, and forming a plurality of second electrodes of the plurality of capacitors, the plurality of second electrodes comprising an electrically discontinuous inner metal conductor located between the plurality of terminals and the first electrode.

7. A method comprising:

providing an integrated circuit having a plurality of terminals for making electrical connection to the integrated circuit;

providing at least one device adjacent a periphery of the integrated circuit, a portion of the at least one device comprising a first metal conductor extending entirely around the integrated circuit to form an edge seal for protecting the integrated circuit during die singulation; and

coupling the at least one device to a functional circuit within the integrated circuit by routing the first metal conductor to the functional circuit, the functional circuit implementing non-test functions within the integrated circuit by using the at least one device.

12. The method of claim 7 further comprising:

forming the at least one device as a plurality of capacitors comprising a common first electrode comprising a continuous outer metal conductor around the periphery of the integrated circuit, and a plurality of second electrodes of the plurality of capacitors comprising an electrically discontinuous metal conductor located between the plurality of terminals and the first electrode.

8. The method of claim 8 further comprising:

forming the at least one device between an outer edge of the integrated circuit and the plurality of terminals.

9. The method of claim 8 further comprising:

forming the at least one device as a capacitor.

10. The method of claim 8 further comprising:

forming the at least one device as an inductor.

11. The method of claim 10 further comprising:

forming the inductor with a continuous metal conductor having a first end electrically connected to a first terminal of the functional circuit and a second end electrically connected to a second terminal of the functional circuit, the inductor looping around the periphery of the integrated circuit at least once.

13. An integrated circuit comprising:

at least one device adjacent an outer edge of the integrated circuit, the at least one device comprising a metal conductor surrounding the outer edge of the integrated circuit for forming an edge seal for protecting the integrated circuit during die singulation; and

a functional circuit within the integrated circuit having a first terminal connected to a first portion of the at least one device and having a second terminal connected to a second portion of the at least one device, the at least one device providing a reactance value to the functional circuit for non-test operational use by the functional circuit.

14. The integrated circuit of claim 13 wherein the at least one device is an inductor comprising a stack of conductive layers.

15. The integrated circuit of claim 14 wherein the stack of conductive layers of the inductor loops within the outer edge of the integrated circuit more than three hundred sixty degrees.

16. The integrated circuit of claim 13 wherein the at least one device is a capacitor.

17. The integrated circuit of claim 16 wherein the capacitor further comprises:

a first metal electrode encircling the outer edge of the integrated circuit and having at least one opening, the first metal electrode connected to the functional circuit at the first terminal, the first metal electrode having an opening therein within a portion that encircles the outer edge of the integrated circuit, the first metal electrode forming a first electrode of the capacitor that is connected to the functional circuit; and

a second metal electrode encircling the outer edge of the integrated circuit between the outer edge and the first metal electrode, the second metal electrode extending through the opening of the first metal electrode and connecting to the functional circuit to function as a second electrode of the capacitor.

18. The integrated circuit of claim 17 wherein the opening within the first metal electrode is formed only through an underlying portion of the first metal electrode.

19. The integrated circuit of claim 13 wherein the at least one device further comprises a plurality of capacitors, each coupling capacitance to the functional circuit during non-testing operation of the integrated circuit.

20. The integrated circuit of claim 13 further comprising

a plurality of capacitors comprising a common first electrode comprising a continuous outer metal conductor around the outer edge of the integrated circuit, and a plurality of second electrodes of the plurality of capacitors comprising an electrically discontinuous inner metal conductor separated from the first electrode by a dielectric.