DETERMINING THE PLACEMENT OF SEMICONDUCTOR COMPONENTS ON AN INTEGRATED CIRCUIT
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Abstract
Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.
32 Citations
24 Claims
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1-21. -21. (canceled)
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22. A semiconductor device, comprising:
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a semiconductor die having an array of solder bumps formed on a surface of the semiconductor die; a first region surrounding a first solder bump in the array of solder bumps, wherein the first region is susceptible to radiation emitted from solder deposited on the first solder bump; a radiation-insensitive standard cell located inside the first region; and a radiation-sensitive standard cell located outside the first region. - View Dependent Claims (23, 24)
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Specification