CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE
First Claim
1. A method of manufacturing a chip stack package comprising:
- preparing a plurality of chips having an electrode pad and a first through-hole that penetrates the electrode pad;
forming adhesive layers on the chips, wherein each of the adhesive layers includes a second through-hole that exposes the first through-hole;
stacking the chips having the adhesive layers such that the first through-holes are aligned on a seed layer of a substrate, the substrate having a wiring pattern and the seed layer disposed on the wiring pattern; and
filling the first through-holes and the second through-holes with conductive material using a plating process so as to form a plug that electrically connects the chips to one another.
1 Assignment
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Accused Products
Abstract
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.
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Citations
20 Claims
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1. A method of manufacturing a chip stack package comprising:
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preparing a plurality of chips having an electrode pad and a first through-hole that penetrates the electrode pad; forming adhesive layers on the chips, wherein each of the adhesive layers includes a second through-hole that exposes the first through-hole; stacking the chips having the adhesive layers such that the first through-holes are aligned on a seed layer of a substrate, the substrate having a wiring pattern and the seed layer disposed on the wiring pattern; and filling the first through-holes and the second through-holes with conductive material using a plating process so as to form a plug that electrically connects the chips to one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of manufacturing a chip stack package comprising:
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forming a first chip structure, the first chip structure including; a substrate having a wiring pattern and a seed layer formed on the wiring pattern; a plurality of first chips having a first electrode pad and a first through-hole that penetrates the first electrode pad, wherein the first chips are stacked such that the first through-holes are aligned on the seed layer of the substrate; a plurality of first adhesive layers interposed between the substrate and the first chips and between the first chips, each of the first adhesive layers having a second through-hole that exposes the first through-hole; and a first plug disposed in the first through-holes and the second through-holes and electrically connecting the first electrode pads of the first chips to the wiring pattern of the substrate; forming a redistribution layer on an uppermost chip of the first chip structure, the redistribution layer connected to the first plug; forming a second chip structure, the second chip structure including; a plurality of second chips having a second electrode pad and a third through-hole that penetrates the second electrode pad, wherein the second chips are stacked such that the third through-holes are aligned on the redistribution layer; a plurality of second adhesive layers interposed between the second chips, each of the second adhesive layers having a fourth through-hole that exposes the third through-hole; and a second plug disposed in the third through-holes and the fourth through-holes and electrically connecting the second electrode pads of the second chips to one another; and adhering the second chip structure on the redistribution layer so as to connect the redistribution layer to the second plug. - View Dependent Claims (12, 13, 14, 15)
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16. A chip stack package comprising:
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a substrate having a wiring pattern and a seed layer formed on the wiring pattern; a plurality of chips having an electrode pad and a first through-hole that penetrates the first electrode pad, wherein the chips are stacked such that the first through-holes are aligned on the seed layer of the substrate; a plurality of adhesive layers interposed between the substrate and one of the chips and between the first chips, each of the adhesive layers having a second through-hole that exposes the first through-hole; and a first plug disposed in the first through-holes and the second through-holes and electrically connecting the first electrode pads of the first chips to the wiring pattern of the substrate. - View Dependent Claims (17, 18, 19, 20)
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Specification