CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE

• US 20080230923A1
• Filed: 03/19/2008
• Published: 09/25/2008
• Est. Priority Date: 03/19/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Ho-Jin, JO, Cha-Jea, CHOI, Ju-Il, LEE, In-Young, KIM, Nam-Seog, CHUNG, Myung-Kee, SHIN, Chang-Woo, KIM, Seok-Ho
• Application Number:
  US12/051,619
• Publication Number:
  US 20080230923A1
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/244 Connecting portions
• CPC Class Codes: H01L 2224/245 Material
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Claims

1. A method of manufacturing a chip stack package comprising:

preparing a plurality of chips having an electrode pad and a first through-hole that penetrates the electrode pad;

forming adhesive layers on the chips, wherein each of the adhesive layers includes a second through-hole that exposes the first through-hole;

stacking the chips having the adhesive layers such that the first through-holes are aligned on a seed layer of a substrate, the substrate having a wiring pattern and the seed layer disposed on the wiring pattern; and

filling the first through-holes and the second through-holes with conductive material using a plating process so as to form a plug that electrically connects the chips to one another.

2. The method of claim 1, wherein a cross-sectional area of a portion of the plug in the second through-holes is larger than a cross-sectional area of a portion of the plug in the first through-holes.

3. The method of claim 1, wherein the chips are stacked such that the electrode pads face upward.

4. The method of claim 1, wherein the chips are stacked such that the electrode pads face downward.

5. The method of claim 1, wherein at least one of the chips is stacked such that the electrode pads face upward and at least one of the chips is stacked such that the electrode pads face downward.

6. The method of claim 1, wherein filling the first through-holes comprises growing the conductive material from the seed layer in a direction substantially parallel to a direction of stacking of the chips to form the plug.

7. The method of claim 1, wherein preparing the chips comprises:

forming a first insulation layer on an upper surface of a wafer having a circuit pattern formed thereon, the first insulation layer exposing at least a portion of the electrode pad;

forming a recess that penetrates the electrode pad at the upper surface of the wafer;

planarizing a lower surface of the wafer until the recess is exposed to form the first through-hole that penetrates the wafer;

forming a second insulation layer on an inner surface of the first through-hole and the lower surface of the wafer; and

cutting the wafer to form the chips.

8. The method of claim 7, wherein a diameter of the first through-hole is smaller than a diameter of the portion of the electrode pad exposed by the first insulation layer.

9. The method of claim 7, further comprising forming a wiring that connects the electrode pad to the circuit pattern of each of the chips so as to adjust alignment positions of the electrode pads of the chips.

10. The method of claim 7, further comprising forming a diffusion barrier layer on the second insulation layer.

11. A method of manufacturing a chip stack package comprising:

forming a first chip structure, the first chip structure including;

a substrate having a wiring pattern and a seed layer formed on the wiring pattern;

a plurality of first chips having a first electrode pad and a first through-hole that penetrates the first electrode pad, wherein the first chips are stacked such that the first through-holes are aligned on the seed layer of the substrate;

a plurality of first adhesive layers interposed between the substrate and the first chips and between the first chips, each of the first adhesive layers having a second through-hole that exposes the first through-hole; and

a first plug disposed in the first through-holes and the second through-holes and electrically connecting the first electrode pads of the first chips to the wiring pattern of the substrate;

forming a redistribution layer on an uppermost chip of the first chip structure, the redistribution layer connected to the first plug;

forming a second chip structure, the second chip structure including;

a plurality of second chips having a second electrode pad and a third through-hole that penetrates the second electrode pad, wherein the second chips are stacked such that the third through-holes are aligned on the redistribution layer;

a plurality of second adhesive layers interposed between the second chips, each of the second adhesive layers having a fourth through-hole that exposes the third through-hole; and

a second plug disposed in the third through-holes and the fourth through-holes and electrically connecting the second electrode pads of the second chips to one another; and

adhering the second chip structure on the redistribution layer so as to connect the redistribution layer to the second plug.

12. The method of claim 11, wherein forming the second chip structure comprises:

forming a first metal layer having a first ionization tendency on a sacrificial substrate;

forming a second metal layer having a second ionization tendency smaller than the first ionization tendency on the first metal layer;

preparing the second chips having the third through-hole that penetrates the second electrode pad;

forming the second adhesive layers on the second chips, respectively, the second adhesive layers having the fourth through-hole that exposes the third through-hole;

stacking the second chips including the second adhesive layers formed thereon such that the third through-holes are aligned on the second metal layer;

filling up the third through-holes and the fourth through-holes with conductive material by a plating process using the second metal layer as a seed to form the second plug; and

selectively removing the first metal layer using a difference of the ionization tendencies of the first metal layer and the second metal layer.

13. The method of claim 12, wherein the first metal layer comprises tin silver (SnAg), tin (Sn), tin copper (SnCu) or indium (In), the second metal layer comprises silver (Ag) or gold (Au), and an electrolyte solution for selectively removing the first metal layer comprises a sulfuric acid solution, a nitric acid solution or a hydrogen peroxide solution.

14. The method of claim 11, wherein forming the second chip structure comprises:

forming a first metal layer on a sacrificial substrate;

oxidizing at least a portion of the first metal layer;

forming a second metal layer on the oxidized first metal layer;

preparing the second chips having the third through-holes that penetrate the second electrode pads;

forming the second adhesive layers on the second chips, respectively, each of the second adhesive layers having the fourth through-hole that exposes the third through-hole;

stacking the second chips including the second adhesive layers formed thereon such that the third through-holes are aligned on the second metal layer;

filling up the third through-holes and the fourth through-holes with conductive material by a plating process using the second metal layer as a seed to form the second plug; and

separating the oxidized first metal layer from the second metal layer.

15. The method of claim 14, wherein the first and second metal layers comprise nickel (Ni), chromium (Cr) or gold (Au).

16. A chip stack package comprising:

a substrate having a wiring pattern and a seed layer formed on the wiring pattern;

a plurality of chips having an electrode pad and a first through-hole that penetrates the first electrode pad, wherein the chips are stacked such that the first through-holes are aligned on the seed layer of the substrate;

a plurality of adhesive layers interposed between the substrate and one of the chips and between the first chips, each of the adhesive layers having a second through-hole that exposes the first through-hole; and

a first plug disposed in the first through-holes and the second through-holes and electrically connecting the first electrode pads of the first chips to the wiring pattern of the substrate.

17. The chip stack package of claim 16, wherein a cross-sectional area of a portion of the plug in the second through-holes is larger than a cross-sectional area of a portion of the plug in the first through-holes.

18. The chip stack package of claim 16, wherein each of the chips comprises an insulation layer that exposes the electrode pad on a surface of the chip.

19. The chip stack package of claim 18, wherein each of the chips further comprises a diffusion barrier layer on the insulation layer.

20. The chip stack package of claim 16, the chips are stacked such that the electrode pads face upward.