Method for calibrating semiconductor device tester

• US 20080231297A1
• Filed: 08/06/2007
• Published: 09/25/2008
• Est. Priority Date: 08/10/2006
• Status: Active Grant

• Current Assignee: UniTest Inc.
• Original Assignee: UniTest Inc.
• Inventors: Kang, Jong Koo
• Granted Patent: US 7,656,178 B2
• Time in Patent Office: Days
• US Class Current: 324/755
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937

Abstract

A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.

Claims

1. A deskew calibration method for removing a skew of a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of:

(a) aligning a plurality of output signals of the plurality of output channels with reference to a drive signal of one of the plurality of drive channels using a first calibration board wherein the first calibration board connects the one of the plurality of drive channels to the plurality of the output channels;

(b) aligning a plurality of drive signals of the plurality of drive channels with reference to the plurality of aligned output signals using a second calibration board wherein second calibration board respectively connects the plurality of drive channels to the plurality of output channels; and

(c) aligning a plurality of input signals with reference to the plurality of aligned output signals using a DUT interface board wherein the DUT interface board respectively connects the plurality of input channels to the plurality of output channels.

2. The method in accordance with claim 1, wherein the step (a) comprises:

(a-1) aligning the plurality of output signals of the plurality of output channels by applying a pulse signal to the one of the plurality of drive channels; and

(a-2) aligning the plurality of output signals of the plurality of output channels by applying a PRBS signal to the one of the plurality of drive channels.

3. The method in accordance with claim 1, wherein the step (b) comprises:

(b-1) aligning the plurality of drive signals of the plurality of drive channels by applying a pulse signal to the plurality of drive channels; and

(b-2) aligning the plurality of drive signals of the plurality of drive channels by applying a PRBS signal to the plurality of drive channels.

4. The method in accordance with claim 1, wherein the step (c) comprises:

(c-1) aligning the plurality of input signals by applying a pulse signal to the plurality of input channels; and

(c-2) aligning the plurality of input signals by applying a PRBS signal to the plurality of input channels.

5. A vernier calibration method for calibrating a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of:

(a) mounting a second calibration board respectively connecting the plurality of drive channels to the plurality of input channels;

(b) generating a lookup table for the plurality of drive channels by fixing a delay value of a deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the drive channels;

(c) generating a lookup table for the plurality of output channels by fixing a delay value of a deskew of the plurality of drive channels and varying a delay code value of a deskew of the plurality of the output channels;

(d) mounting a DUT interface board respectively connecting the plurality of input channels to the plurality of output channels; and

(e) generating a lookup table for the plurality of input channels by fixing the delay value of the deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the input channels.

6. The method in accordance with claim 5, wherein the step (b) comprises:

(b-1) obtaining an actual delay according to each of the delay code values by varying the delay code of the deskew of the plurality of drive channels;

(b-2) selecting the actual delay closest to a delay to be programmed in the deskew of the plurality of drive channels; and

(b-3) generating the lookup table for the plurality of drive channels using the actual delay selected in the step (b-2) and the code value corresponding thereto.

7. The method in accordance with claim 5, wherein the step (C) comprises:

(c-1) obtaining an actual delay according to each of the delay code values by varying the delay code of the deskew of the plurality of output channels;

(c-2) selecting the actual delay closest to a delay to be programmed in the deskew of the plurality of output channels; and

(c-3) generating the lookup table for the plurality of output channels using the actual delay selected in the step (c-2) and the code value corresponding thereto.

8. The method in accordance with claim 5, wherein the step (e) comprises:

(e-1) obtaining an actual delay according to each of the delay code values by varying the delay code of the deskew of the plurality of input channels;

(e-2) selecting the actual delay closest to a delay to be programmed in the deskew of the plurality of input channels; and

(e-3) generating the lookup table for the plurality of input channels using the actual delay selected in the step (e-2) and the code value corresponding thereto.

9. The method in accordance with claim 6, further comprising aligning the delay code values according to the selected actual delay closest to the delay to be programmed.

10. The method in accordance with claim 7, further comprising aligning the delay code values according to the selected actual delay closest to the delay to be programmed.

11. The method in accordance with claim 8, further comprising aligning the delay code values according to the selected actual delay closest to the delay to be programmed.

12. The method in accordance with claim 6, wherein the step (b-1) comprises:

(b-1-1) alternately applying a first logic value and a second logic value to the second calibration board, the second logic value being an inverted value of the first logic value;

(b-1-2) measuring a frequency of a return signal including the first logic value and the second logic value having passed through the IO channel; and

(b-1-3) obtaining the actual delay from the frequency.

13. The method in accordance with claim 7, wherein the step (c-1) comprises:

(c-1-1) alternately applying a first logic value and a second logic value to the second calibration board, the second logic value being an inverted value of the first logic value;

(c-1-2) measuring a frequency of a return signal including the first logic value and the second logic value having passed through the IO channel; and

(c-1-3) obtaining the actual delay from the frequency.

14. The method in accordance with claim 8, wherein the step (e-1) comprises:

(e-1-1) alternately applying a first logic value and a second logic value to the DUT interface board, the second logic value being an inverted value of the first logic value;

(e-1-2) measuring a frequency of a return signal including the first logic value and the second logic value having passed through the IO channel; and

(e-1-3) obtaining the actual delay from the frequency.

15. A calibration method of a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of:

(a) aligning a plurality of output signals of the plurality of output channels with reference to a drive signal of one of the plurality of drive channels using a first calibration board wherein the first calibration board connects the one of the plurality of drive channels to the plurality of the output channels;

(b) aligning a plurality of drive signals of the plurality of drive channels with reference to the plurality of aligned output signals using a second calibration board wherein second calibration board respectively connects the plurality of drive channels to the plurality of output channels;

(c) aligning a plurality of input signals with reference to the plurality of aligned output signals using a DUT interface board wherein the DUT interface board respectively connects the plurality of input channels to the plurality of output channels;

(d) generating a lookup table for the plurality of drive channels by fixing a delay value of a deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the drive channels after mounting the second calibration board;

(e) generating a lookup table for the plurality of output channels by fixing a delay value of a deskew of the plurality of drive channels and varying a delay code value of a deskew of the plurality of the output channels; and

(f) generating a lookup table for the plurality of input channels by fixing the delay value of the deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the input channels after mounting the DUT interface board.