TESTING METHOD USING A SCALABLE PARAMETRIC MEASUREMENT MACRO
First Claim
1. A testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:
- testing chips after manufacture;
during said testing of said chips, taking parametric measurements from said on-chip parametric measurement macros, said parametric measurements comprising actual values for at least one of an electrical parameter and a physical parameter;
determining yield loss based on results of said testing; and
correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements.
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Abstract
Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.
66 Citations
35 Claims
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1. A testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:
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testing chips after manufacture; during said testing of said chips, taking parametric measurements from said on-chip parametric measurement macros, said parametric measurements comprising actual values for at least one of an electrical parameter and a physical parameter; determining yield loss based on results of said testing; and correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:
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testing chips after manufacture; during said testing of said chips, taking parametric measurements from said on-chip parametric measurement macros, said parametric measurements comprising actual values for at least one of an electrical parameter and a physical parameter; determining yield loss based on results of said testing; and correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:
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testing chips from a lot after manufacture; during said testing of said chips, taking parametric measurements from at least one of said on-chip parametric measurement macros on each of said chips, said parametric measurements comprising actual values for at least one of an electrical parameter and a physical parameter; identifying faulty chips, wherein any chip, having a predetermined number of said parametric measurements that do not meet predetermined pass/fail criteria, is considered faulty; and discarding said faulty chips from said lot. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 35)
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27. A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:
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testing chips from a lot after manufacture, during said testing of said chips, taking parametric measurements from at least one of said on-chip parametric measurement macros on each of said chips, said parametric measurements comprising actual values for at least one of an electrical parameter and a physical parameter; identifying faulty chips, wherein any chip, having a predetermined number of said parametric measurements that do not meet predetermined pass/fail criteria, is considered faulty; and discarding said faulty chips from said lot. - View Dependent Claims (28, 29, 31, 32, 33, 34)
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30. (canceled)
Specification