Structure for modeling stress-induced degradation of conductive interconnects
First Claim
1. A structure representative of a conductive interconnect in a microelectronic element for purposes of modeling stress-induced degradation, comprising:
- a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface;
a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end;
a lower element consisting essentially of at least one of conductive or semiconductive material in contact with said bottom end of said lower via;
an upper metallic via in at least substantial vertical alignment with said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times than said length and at least about ten times smaller than said width; and
an upper metallic line element in contact with said top end of said upper metallic via.
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Accused Products
Abstract
A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
22 Citations
10 Claims
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1. A structure representative of a conductive interconnect in a microelectronic element for purposes of modeling stress-induced degradation, comprising:
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a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface; a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end; a lower element consisting essentially of at least one of conductive or semiconductive material in contact with said bottom end of said lower via; an upper metallic via in at least substantial vertical alignment with said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times than said length and at least about ten times smaller than said width; and an upper metallic line element in contact with said top end of said upper metallic via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification