METHOD AND SYSTEM FOR SIMULTANEOUS TRANSMISSION AND RECEPTION OF FM SIGNALS UTILIZING A DDFS CLOCKED BY AN RFID PLL

• US 20080231422A1
• Filed: 05/29/2007
• Published: 09/25/2008
• Est. Priority Date: 03/19/2007
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Rofougaran, Ahmadreza
• Granted Patent: US 7,915,999 B2
• Time in Patent Office: Days
• US Class Current: 340/10.1
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/156 One or more switches are realised in the feedback circuit of the amplifier stage
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals

Abstract

Aspects of a method and system for simultaneous transmission and reception of FM signals utilizing a DDFS clocked by an RFID PLL are provided. In this regard, a plurality of signals utilized to transmit or receive FM communication may be generated by clocking a plurality of DDFSs via a signal generated to enable RFID communication.

The DDFSs may be controlled via one or more control words, which may be generated by a processor. In this regard, the control words may determine a frequency and/or phase of the signals output by the DDFSs. The control words may be adjusted to maintain a constant phase and/or frequency at the DDFS outputs in spite of changes to the signal clocking the DDFS. Accordingly, signals of two or more frequencies may be generated by the DDFSs to allow simultaneous transmission and reception of FM signals.

Claims

1. A method for signal processing, the method comprising:

generating a first signal to enable transmission and/or reception of RFID signals; and

generating, via a plurailty of DDFSs, a corresponding plurality of signals which enable simultaneous transmission and reception of frequency modulated signals, wherein said plurality of DDFSs are clocked by said generated first signal.

2. The method according to claim 1, comprising generating one or more control words input to said plurality of DDFSs that control said generation of said plurality of signals by said plurality of DDFSs.

3. The method according to claim 1, wherein said transmission occurs at a first frequency and said reception occurs at a second frequency.

4. The method according to claim 1, comprising adjusting one or more control words input to said plurality of DDFSs, which control. said generation of said plurality of signals by said plurality of DDFSs, to compensate for changes in a frequency of said first signal.

5. The method according to claim 1, wherein a frequency of said first signal is within one of the following bands:

868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and/or 5.725 to 5.875 GHz.

6. The method according to claim 1, wherein a frequency of each of said generated plurality of signals is within a frequency band of 60 MHz to 130 MHz.

7. The method according to claim 1, wherein each of said generated plurality of signals comprises an in-phase component and a quadrature-phase component.

8. The method according to claim 1, comprising generating said first signal via a phase locked loop.

9. The method according to claim 8, wherein said phase locked loop operates at a fixed frequency.

10. A system for signal processing, the system comprising:

one or more circuits that generate a first signal to enable transmission and/or reception of RFID signals; and

said one or more circuits clocks a plurality of DDFSs via said generated first signal to generate a corresponding plurality of signals, which enable simultaneous transmission and reception of frequency modulated signals.

12. The system according to claim 12, wherein said FM transmission occurs at a first frequency and said FM reception occurs at a second frequency.

11. The system according to claim 12, wherein said one or more circuits generate one or more control words input to said plurality of DDFSs that control said generation of said plurality of signals by said plurality of DDFS.

13. The system according to claim 12, wherein said one or more circuits adjusts one or more control words input to said plurality of DDFSs, which control said generation of said plurality of signals by said plurality of DDFSs, to compensate for changes in a frequency of said first signal

14. The system according to claim 12, wherein a frequency of said first signal is within one of the following frequency bands:

868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and 5.725 to 5.875 GHz.

15. The system according to claim 12, wherein a frequency of each of said generated plurality of signals is within a frequency band of 60 MHz to 130 MHz.

16. The system according to claim 12, wherein each of said generated plurality of signals comprises an in phase component and a quadrature component.

17. The system according to claim 12, wherein said one or more circuits comprise a phase locked loop that generates said first signal.

19. A machine-readable storage having stored thereon, a computer program having at least one code section for signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

generating a first signal to enable transmission and/or reception of RFID signals; and

generating, via a plurailty of DDFSs, a corresponding plurality of signals which enable simultaneous transmission and reception of frequency modulated signals, wherein said plurality of DDFSs are clocked by said generated first signal.

18. The system according to claim 21, wherein said phase locked loop operates at a fixed frequency.

20. The machine-readable storage according to claim 19, wherein the at least one code section enables generating one or more control words input to said plurality of DDFSs that control said generation of said plurality of signals by said plurality of DDFSs.

21. The machine-readable storage according to claim 19, wherein said transmission occurs at a first frequency and said reception occurs at a second frequency.

22. The machine-readable storage according to claim 19, wherein the at least one code section enables adjusting one or more control words input to said plurality of DDFSs, which control said generation of said plurality of signals by said plurality of DDFSs, to compensate for changes in a frequency of said first signal.

23. The machine-readable storage according to claim 19, wherein a frequency of said first signal is within one of the following bands:

868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and/or 5.725 to 5.875 GHz.

24. The machine-readable storage according to claim 19, wherein a frequency of each of said generated plurality of signals is within a frequency band of 60 MHz to 130 MHz.

25. The machine-readable storage according to claim 19, wherein each of said generated plurality of signals comprises an in-phase component and a quadrature-phase component.

26. The machine-readable storage according to claim 19, wherein the at least one code section enables generating said first signal via a phase locked loop.

27. The machine-readable storage according to claim 26, wherein said phase locked loop operates at a fixed frequency.