EFFICIENT SPATIAL MODULATOR SYSTEM
First Claim
4-1. The spatial light modulator system of claim 1, wherein the spatial light modulator includes a tiltable micro mirror plate supported by a substrate and one or more electrodes under the micro mirror plate.
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Abstract
A spatial light modulator system includes an array of pixel cells each that includes two static random access memory (SRAM) devices configured to store digital data and output a first voltage signal in response to the digital data, a level shifter configured to receive the first voltage signal from at least one of the two SRAM devices and output a second voltage signal and a spatial light modulator configured to output light in an on direction or an off direction in response to the second voltage signal.
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Citations
31 Claims
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4-1. The spatial light modulator system of claim 1, wherein the spatial light modulator includes a tiltable micro mirror plate supported by a substrate and one or more electrodes under the micro mirror plate.
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15. A spatial light modulator system, comprising:
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an array of pixel cells each comprising; two static random access memory (SRAM) devices each configured to store digital data and output a first voltage signal in response to the digital data; a level shifter configured to receive the first voltage signal from at least one of the two SRAM devices and output a second voltage signal; and a tiltable micro mirror plate supported by a substrate and one or more electrodes under the micro mirror plate, wherein the one or more electrodes are configured to receive the second voltage signal from the level shifter, wherein the micro mirror plate is configured to tilt a predetermined position in response to the second voltage signal. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method for controlling an array of spatial light modulators (SLMs) in response to a digital image, comprising:
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dividing a color field of the digital image into a plurality of bit planes including a first bit plane, a second bit plane, and a third bit plane; displaying the first bit plane by controlling an SLM in the array to a predetermined position; writing data associated with the second bit plane to a first static random access memory (SRAM) device and data associated with the third bit plane to a second SRAM device during the displaying of the first bit plane; after the displaying of the first bit plane, displaying the second bit plane by controlling the SLM in the array to the predetermined position in accordance with the data written to the first SRAM device; and after the displaying of the second bit plane, displaying the third bit plane by controlling the SLM in the array to the predetermined position in accordance with the data written to the second SRAM device. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification