Inverter Circuit with Distributed Energy Stores

• US 20080232145A1
• Filed: 07/31/2006
• Published: 09/25/2008
• Est. Priority Date: 08/26/2005
• Status: Abandoned Application

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Sommer, Rainer, Hiller, Marc
• Application Number:
  US12/064,897
• Publication Number:
  US 20080232145A1
• Time in Patent Office: Days
• US Class Current: 363/56.01
• CPC Class Codes: H02H 7/1225 responsive to internal faults, e.g. shoot-through avoiding shoot-through H02M1/38
• CPC Class Codes: H02M 1/325 with means for allowing continuous operation despite a fault, i.e. fault tolerant converters
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage

Abstract

The invention relates to a rectifier circuit comprising a phase module (110) with at least one upper and one lower rectifier valve (T1, . . . , T6), said phase module (100) being electrically connected on the DC side to a positive and a negative DC busbar (P0, N0), each rectifier valve (T1, . . . , T6) having at least two bipolar subsystems (10) electrically connected in series. According to the invention, a protection component (12) is connected in parallel to the connector contacts (X1, X2) of each subsystem (10). A rectifier circuit is thus obtained with distributed energy stores which can be operated redundantly in case of fault.

Claims

1-18. -18. (canceled)

19. An inverter circuit, comprising:

at least one phase module connected between a positive and a negative DC busbar on a DC side of an inverter and having two converter valves, each of the converter valves including at least two serially connected two-terminal subsystems having connecting terminals, and

a plurality of protective components connected to the subsystems in one-to-one correspondence, wherein the protective components are connected in parallel with the connecting terminals of the subsystems.

20. The inverter circuit of claim 19, wherein each two-terminal subsystem comprises two serially connected turn-off semiconductor switches, a unipolar storage capacitor connected in parallel with the serially connected turn-off semiconductor switches, and two diodes, with each of the two diodes being connected antiparallel with a corresponding one of the two turn-off semiconductor switches.

21. The inverter circuit of claim 20, wherein one the connecting terminals is connected to a center tap of the serially connected turn-off semiconductor switches and the other connecting terminal is connected to an end tap of the serially connected turn-off semiconductor switches.

22. The inverter circuit of claim 19, wherein each two-terminal subsystem comprises four serially connected turn-off semiconductor switches forming a bridge circuit having AC-side terminals forming the connecting terminals and DC-side terminals, a storage capacitor connected to the DC-side terminals, and four diodes, with each of the four diodes being connected antiparallel with a corresponding one of the four turn-off semiconductor switches.

23. The inverter circuit of claim 19, wherein the protective component is implemented as a diode.

24. The inverter circuit of claim 19, wherein the protective component is implemented as a thyristor having an anode and a gate, wherein the anode is connected to the gate via an active clamping circuit.

25. The inverter circuit of claim 19, wherein the protective component comprises two diodes connected in series back-to-back.

26. The inverter circuit of claim 19, wherein the protective component is implemented as a thyristor having an anode and a gate, wherein the anode is connected to the gate via Zener diodes and decoupling diodes.

27. The inverter circuit of claim 24, further comprising a gate resistor connected to the gate of the thyristor.

28. The inverter circuit of claim 26, further comprising a gate resistor connected to the gate of the thyristor.

29. The inverter circuit of claim 24, further comprising an RC circuit connected in parallel with the anode and a cathode of the thyristor.

30. The inverter circuit of claim 26, further comprising an RC circuit connected in parallel with the anode and a cathode of the thyristor.

31. The inverter circuit of claim 20, wherein the turn-off semiconductor switches are implemented as insulated gate bipolar transistors.

32. The inverter circuit of claim 20, wherein the turn-off semiconductor switches are implemented as MOS field effect transistors.

33. The inverter circuit of claim 20, wherein the turn-off semiconductor switches are implemented as gate turn-off thyristors.

34. The inverter circuit of claim 20, wherein the turn-off semiconductor switches are implemented as integrated gate commutated thyristors.

35. A control method for an inverter circuit with at least one phase module having two converter valves and being connected between a positive a negative DC busbar on a DC side of an inverter and, each converter valve including at least two serially connected two-terminal subsystems, said control method comprising the following steps:

a). identifying a faulty phase module having a failed subsystem,

b). driving at least one additional subsystem of the identified faulty phase module into a first switching state for a predetermined time period, and

c). driving at least one subsystem of a fault-free phase module into a second switching state for another predetermined time period.

36. The control method of claim 35, further comprising the step of repeating steps b) and c) at least once, with a predetermined time interval being observed between repetitions.

37. The control method of claim 35, further comprising the steps of determining a corresponding voltage across a storage capacitor of each subsystem, comparing the determined voltages with a preset tolerance band, and identifying a subsystem as having failed if the determined voltage lies outside the preset tolerance band.