Efficient Power Supplies and Methods for Creating Such

• US 20080232146A1
• Filed: 01/23/2008
• Published: 09/25/2008
• Est. Priority Date: 03/23/2007
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Amaro, Michael G., Korsunsky, Roman, Thomas, Ted
• Application Number:
  US12/018,645
• Publication Number:
  US 20080232146A1
• Time in Patent Office: Days
• US Class Current: 363/127
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Various embodiments of the present invention provide rectifier controllers, power supplies and methods for operating such. As one example, a rectifier controller circuit is disclosed that includes a transistor, a phase locked loop circuit, a period counter and a combinational logic circuit. One leg of the transistor is electrically coupled to a switch node of a power supply, and is in parallel to a diode of the power supply. The phase locked loop circuit receives a signal representing a voltage at the switch node, and is operable to synchronize to a period of the signal representing the voltage at the switch node. The period counter divides the period of the signal representing the voltage at the switch node into segments. The combinational logic circuit is operable to turn the transistor on an assertion delay period after a first transition of the signal representing the voltage at the switch node, and to turn the transistor off before a second transition of the signal representing the voltage at the switch node based on the period counter.

Claims

1. A rectifier controller circuit, the circuit comprising:

a transistor, wherein one leg of the transistor is electrically coupled to a switch node of a power supply, and wherein the transistor is in parallel to a diode of the power supply;

a phase locked loop circuit, wherein the phase locked loop circuit receives a signal representing a voltage at the switch node, and wherein the phase locked loop circuit is operable to synchronize to a period of the signal representing the voltage at the switch node;

a period counter, wherein the period counter divides the period of the signal representing the voltage at the switch node into segments; and

a combinational logic circuit, wherein the combinational logic circuit is operable to turn the transistor on an assertion delay period after a first transition of the signal representing the voltage at the switch node, and to turn the transistor off before a second transition of the signal representing the voltage at the switch node based on the period counter.

2. The rectifier controller circuit of claim 1, wherein the first transition of the signal representing the voltage at the switch node is a falling edge, and wherein the second transition of the signal representing the voltage at the switch node is a rising edge.

3. The rectifier controller circuit of claim 1, wherein the period counter is set to a known value coincident with the second transition.

4. The rectifier controller of claim 1, wherein the phase locked loop circuit, the period counter and the combinational logic circuit are implemented on the same semiconductor die.

5. The rectifier controller of claim 4, wherein the transistor, the phase locked loop circuit, the period counter and the combinational logic circuit are implemented on the same semiconductor die.

6. The rectifier controller circuit of claim 1, wherein the combinational logic circuit is further operable to turn the transistor off whenever the phase locked loop circuit indicates a loss of lock.

7. The rectifier controller circuit of claim 1, wherein the combinational logic circuit is further operable to turn the transistor off whenever a system enable is de-asserted.

8. The rectifier controller circuit of claim 1, wherein the power supply is a non-synchronous power supply.

9. The rectifier controller circuit of claim 1, wherein the power supply is a forward converter.

10. A method for improving efficiency in a non-synchronous power supply, the method comprising:

providing a power supply, wherein the power supply includes;

a voltage input electrically coupled to a switch node via a switch, wherein the voltage input supplies current to the switch node whenever the switch is closed; and

a diode, wherein the diode is capable of supplying current to the switch node whenever the switch is open;

providing a rectifier controller circuit, wherein the rectifier controller circuit includes;

a transistor;

a phase locked loop circuit;

a period counter, and

a combinational logic circuit; and

electrically coupling the transistor in parallel to the diode, wherein one leg of the transistor is electrically coupled to the switch node;

electrically coupling the phase lock loop circuit to the switch node, wherein the phase lock loop circuit is operable to synchronize to a period of the signal representing the voltage at the switch node, and wherein the period counter divides the period of the signal representing the voltage at the switch node into segments; and

wherein the combinational logic circuit is operable to turn the transistor on an assertion delay period after a first transition of the signal representing the voltage at the switch node, and to turn the transistor off before a second transition of the signal representing the voltage at the switch node based on the period counter.

11. The method of claim 10, wherein the first transition of the signal representing the voltage at the switch node is a falling edge, and wherein the second transition of the signal representing the voltage at the switch node is a rising edge.

12. The method of claim 10, wherein the method further comprises setting the period counter to a known value coincident with the second transition of the signal representing the voltage at the switch node.

13. The method of claim 10, wherein the combinational logic circuit is further operable to turn the transistor off whenever the phase locked loop circuit indicates a loss of lock.

14. The method of claim 10, wherein the method further comprises:

receiving a system enable signal; and

turning the transistor off whenever the system enable is de-asserted.

15. The method of claim 14, wherein the system enable is electrically coupled to a voltage output of the power supply.

16. A power supply, the power supply comprising:

a voltage input, wherein the voltage input is electrically coupled to a switch node via a switch,

a diode, wherein the diode is capable of supplying current to the switch node whenever the switch is open;

a transistor, wherein one leg of the transistor is electrically coupled to the switch node, and wherein the transistor is in parallel to the diode;

a phase locked loop circuit, wherein the phase locked loop circuit receives a signal representing a voltage at the switch node, and wherein the phase locked loop circuit is operable to synchronize to a period of the signal representing the voltage at the switch node;

a period counter, wherein the period counter divides the period of the signal representing the voltage at the switch node into segments; and

a combinational logic circuit, wherein the combinational logic circuit is operable to turn the transistor on an assertion delay period after a first transition of the signal representing the voltage at the switch node, and to turn the transistor off before a second transition of the signal representing the voltage at the switch node based on the period counter.

17. The power supply of claim 16, wherein the first transition of the signal representing the voltage at the switch node is a falling edge, and wherein the second transition of the signal representing the voltage at the switch node is a rising edge.

18. The power supply of claim 16, wherein the period counter is set to a known value coincident with the second transition of the signal representing the voltage at the switch node.

19. The power supply of claim 16, wherein the phase locked loop circuit, the period counter and the combinational logic circuit are implemented on the same integrated circuit, and wherein the integrated circuit is tailored for addition to an existing power supply design.

20. The power supply of claim 16, wherein the switch is controlled by a DC/DC non-synchronouns controller.