Multi-cell data processor

• US 20080232445A1
• Filed: 03/21/2007
• Published: 09/25/2008
• Est. Priority Date: 03/21/2007
• Status: Active Grant

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Nokia Corporation
• Inventors: Forsell, Martti
• Granted Patent: US 7,856,246 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The exemplary embodiments of this invention provide a data processor having a processor engine composed of a plurality of processor cells, each cell including a local instruction memory and an instruction sequencer and being configured for selective connection with at least one adjacent cell enabling communication between cells. The processor engine is configured to be interposed between a radio frequency section and a baseband section to process data output from the baseband section prior to inputting the processed data to the radio frequency section, and to process signals output from the radio frequency section prior to inputting processed data to the baseband section. A plurality of communication-related functions are mapped into a corresponding plurality of regions of cells, and local instruction memory is configured to store program instructions for implementing all or a part of the associated function. As examples, one function may be a CORDIC function and another function may be a FIR filter function.

Claims

1. A data processor, comprising:

a processor engine comprised of a plurality of processor cells, each cell comprising a local instruction memory and an instruction sequencer and being configured for selective connection with at least one adjacent cell enabling communication between cells, said processor engine configured to be interposed between a radio frequency section and a baseband section to process data output from the baseband section prior to inputting the processed data to the radio frequency section, and to process signals output from the radio frequency section prior to inputting processed data to the baseband section.

2. The data processor as in claim 1, wherein a plurality of functions are mapped into a corresponding plurality of regions of cells, each region comprising at least one cell, and where the local instruction memory of each cell of a region is configured to store program instructions for implementing all or a part of the associated function.

3. The data processor as in claim 2, where one function is a CORDIC function.

4. The data processor as in claim 2, where one function is a FIR filter function.

5. The data processor as in claim 2, where the plurality of functions correspond to functions for implementing a particular radio frequency standard.

6. The data processor as in claim 2, where the plurality of functions correspond to functions for simultaneously implementing a plurality of radio frequency standards.

7. The data processor as in claim 1, where the radio frequency section comprises at least one radio frequency transmitter and at least one radio frequency receiver.

8. The data processor as in claim 1, where the radio frequency section comprises a plurality of radio frequency transmitter and receivers.

9. The data processor as in claim 1, where the plurality of cells are selectively configured into a full mesh topology.

10. The data processor as in claim 1, where the plurality of cells are selectively configured into a full torus topology.

11. The data processor as in claim 1, where each instruction executes in one clock cycle.

12. The data processor as in claim 1, where each cell comprises an intra-cell bus and, coupled to the intra-cell bus, a plurality of ALUs each coupled to the intra-cell bus via an associated register block.

13. The data processor as in claim 2, where a cell within a region of cells comprises balanced code enabling unique control in the region of cells that does not break synchronization between the cells belonging to the region.

14. The data processor as in claim 1, where each cell comprises an I/O unit configured for interfacing to a global I/O system through which the data processor is interfaced to the radio frequency section and to the baseband section.

15. The data processor as in claim 1, embodied in an integrated circuit.

16. The data processor as in claim 1, embodied in a communication device.

17. The data processor as in claim 1, embodied in a multi-mode, multi-frequency band communication device.

18. A method, comprising:

providing a processor engine comprised of a plurality of processor cells, each cell comprising a local instruction memory and an instruction sequencer and being configured for selective connection with at least one adjacent cell enabling communication between cells, said processor engine configured to be interposed between a radio frequency section and a baseband section to process data output from the baseband section prior to inputting the processed data to the radio frequency section, and to process signals output from the radio frequency section prior to inputting processed data to the baseband section;

mapping a plurality of functions into a corresponding plurality of regions of cells, each region comprising at least one cell; and

configuring the local instruction memory of each cell of a region to store program instructions for implementing all or a part of the associated function.

19. The method of claim 18, where one function is a CORDIC function.

20. The method of claim 18, where one function is a FIR filter function.

21. The method of claim 18, where the plurality of functions correspond to functions for implementing a particular radio frequency standard.

22. The method of claim 18, where the plurality of functions correspond to functions for simultaneously implementing a plurality of radio frequency standards.

23. The method of claim 18, where the plurality of cells are selectively configured into a full mesh topology.

24. The method of claim 18, where the plurality of cells are selectively configured into a full torus topology.

25. The method of claim 18, where configuring a cell within a region of cells comprises providing balanced code enabling unique control in the region of cells that does not break synchronization between the cells belonging to the region.

26. A device, comprising a radio frequency section, a baseband section and, interposed between said radio frequency section and said baseband section, a processor engine comprised of a plurality of processor cells, each cell comprising a local instruction memory and an instruction sequencer and being configured for selective connection with at least one adjacent cell enabling communication between cells, said processor engine configured to process data output from the baseband section prior to inputting the processed data to the radio frequency section, and to process signals output from the radio frequency section prior to inputting processed data to the baseband section.

27. The device of claim 26, where a plurality of functions are mapped into a corresponding plurality of regions of cells, each region comprising at least one cell, and where the local instruction memory of each cell of a region is configured to store program instructions for implementing all or a part of the associated function.

28. The device of claim 27, where one function is a CORDIC function, and where another function is a FIR filter function.

29. The device of claim 27, where the plurality of functions correspond to functions for implementing at least one radio frequency standard.

30. The device as in claim 29, where the radio frequency section comprises at least one radio frequency transmitter and at least one radio frequency receiver associated with the at least one radio frequency standard.

31. The device as in claim 26, where the plurality of cells are selectively configured into one of a full mesh topology, a full torus topology, or a limited connectivity topology.

32. The device as in claim 26, where each cell comprises an intra-cell bus and, coupled to the intra-cell bus, a plurality of ALUs each coupled to the intra-cell bus via an associated register block.

33. The device as in claim 26, where a cell within a region of cells comprises balanced code enabling unique control in the region of cells that does not break synchronization between the cells belonging to the region.

34. The device as in claim 26, where each cell comprises an I/O unit configured for interfacing to a global I/O system through which the processor engine is interfaced to the radio frequency section and to the baseband section.

35. The device as in claim 26, where said processor engine is embodied in an integrated circuit.

36. The device as in claim 26, embodied as a single-mode, single-band communication device.

37. The device as in claim 26, embodied as a multi-mode, multi-band communication device.

38. A communication device, comprising:

means for transmitting and receiving radio frequency signals;

means for processing baseband data; and

a processor engine interposed between said means for transmitting and receiving and said means for processing baseband data, said processor engine comprised of a plurality of processor cells, each cell comprising instruction storage and execution means, and further comprising means for selectively connecting to at least one adjacent cell for enabling communication between cells, where a plurality of communication-related functions are mapped into a corresponding plurality of regions of cells, each region comprising at least one cell, and where said instruction storage and execution means of each cell of a region is configured to store program instructions for implementing all or a part of the associated function.

39. The communication device of claim 38, where one function is a CORDIC function, and where another function is a FIR filter function.

40. The communication device of claim 38, where the plurality of functions correspond to functions for implementing at least one radio frequency standard.

41. The communication device of claim 38, where said means for transmitting and receiving radio frequency signals comprises at least one radio frequency transmitter and at least one radio frequency receiver associated with the at least one radio frequency standard.

42. The communication device of claim 38, where said means for transmitting and receiving radio frequency signals comprises a plurality radio frequency transmitters and a plurality of radio frequency receivers associated with a plurality of radio frequency standards.

43. The communication device of claim 38, where the plurality of cells are selectively configured into one of a full mesh topology, a full torus topology, or a limited connectivity topology.

44. The communication device of claim 38, where at least said means for transmitting and receiving radio frequency signals and said processor engine are integrated into a single integrated circuit.

45. The communication device of claim 38, where at least said means for processing baseband data and said processor engine are integrated into a single integrated circuit.

46. The communication device of claim 38, where at least said means for transmitting and receiving radio frequency signals, said means for processing baseband data, and said processor engine are integrated into a single integrated circuit.