MICRODISPLAY PACKAGING SYSTEM

• US 20080233667A1
• Filed: 06/03/2008
• Published: 09/25/2008
• Est. Priority Date: 12/31/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: O'Connor, Michael, Ward-Dolkas, Paul C., Springett, Thomas W.
• Granted Patent: US 8,044,431 B2
• Time in Patent Office: Days
• US Class Current: 438/28
• CPC Class Codes: G02F 1/1333 Constructional arrangements; Manufacturing methodsG02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133308 Support structures for LCD panels, e.g. frames or bezels
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 2201/54 Arrangements for reducing warping-twist
• CPC Class Codes: G02F 2203/60 Temperature independent

Abstract

Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Claims

1-20. -20. (canceled)

21. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures.

22. A method according to claim 21, wherein affixing the base comprises:

applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;

bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and

partially curing the epoxy at least one operating temperature of the imaging elements.

23. A method according to claim 21, wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of a protective cover, and wherein the imaging elements are disposed between the cover and the semiconductor substrate.

24. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate.

25. A method according to claim 24, wherein affixing the base comprises:

affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.

26. A method according to claim 24, wherein affixing the base comprises:

applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;

bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and

partially curing the epoxy at at least one operating temperature of the imaging elements.

27-28. -28. (canceled)