METHOD OF INTEGRATING MEMS STRUCTURES AND CMOS STRUCTURES USING OXIDE FUSION BONDING

• US 20080233672A1
• Filed: 03/20/2007
• Published: 09/25/2008
• Est. Priority Date: 03/20/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation, Nanochip, Inc.
• Original Assignee: Nanochip, Inc.
• Inventors: Heck, John
• Application Number:
  US11/688,808
• Publication Number:
  US 20080233672A1
• Time in Patent Office: Days
• US Class Current: 438/48
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11B 9/1436 with provision for moving the heads or record carriers relatively to each other

Abstract

A method to fabricate a device including a micro-electro-mechanical system structure and a monolithic integrated circuit comprises using a first wafer as a first substrate, fabricating the micro-electro-mechanical system structure on the first substrate, and forming a first oxide layer over the micro-electro-mechanical system structure. The method further comprises using a second wafer as a second substrate, fabricating the monolithic integrated circuit on the second substrate, and forming a second oxide layer over the monolithic integrated circuit. The first wafer and the second wafer are arranged so that the first oxide layer opposes the second oxide layer. The micro-electro-mechanical system structure is aligned with the monolithic integrated circuit, the first oxide layer is contacted with the second oxide layer; and bonded with the second oxide layer.

Claims

1. A method to fabricate a device including a micro-electro-mechanical system structure and a monolithic integrated circuit, comprising:

using a first wafer as a first substrate;

fabricating the micro-electro-mechanical system structure on the first substrate;

forming a first oxide layer over the micro-electro-mechanical system structure;

using a second wafer as a second substrate;

fabricating the monolithic integrated circuit on the second substrate;

forming a second oxide layer over the monolithic integrated circuit;

arranging the first wafer and the second wafer so that the first oxide layer opposes the second oxide layer;

aligning the micro-electro-mechanical system structure with the monolithic integrated circuit;

contacting the first oxide layer with the second oxide layer; and

bonding the first oxide layer and the second oxide layer.

2. The method of claim 1, further comprising:

planarizing the first oxide layer after forming the first oxide layer over the micro-electro-mechanical system structure;

planarizing the second oxide layer after forming the second oxide layer over the monolithic integrated circuit; and

removing the first substrate after bonding the first oxide layer and the second oxide layer.

3. The method of claim 1, wherein bonding the first oxide layer and the second oxide layer includes fusion bonding the first oxide layer and the second oxide layer.

4. The method of claim 2, further comprising:

forming a via through the micro-electro-mechanical system structure to a conductive interconnect of the monolithic integrated circuit; and

forming a conductive material within the via.

5. The method of claim 4, wherein the micro-electro-mechanical system structure is a cantilever having a tip extending from a distal end of the cantilever;

and

wherein when the conductive material is formed within the via, the tip is adapted to electrically communicate with the monolithic integrated circuit.

6. The method of claim 5, further comprising:

removing the first oxide layer over a portion of the cantilever including the distal end prior to planarizing the first oxide layer;

forming a sacrificial layer over the portion of the cantilever;

wherein planarizing the first oxide layer includes planarizing the sacrificial layer.

7. The method of claim 6, wherein the sacrificial layer is copper.

8. The method of claim 6, wherein the monolithic integrated circuit is a complementary-metal-oxide semiconductor circuit.

9. The method of claim 6, further comprising:

removing the sacrificial layer so that the distal end of the cantilever is movable relative to the monolithic integrated circuit.

10. The method of claim 1, further comprising:

forming a barrier layer over the first substrate; and

wherein the barrier layer is disposed between the first substrate and the micro-electro-mechanical system structure.

11. The method of claim 10, wherein the barrier layer comprises silicon dioxide.

12. The method of claim 10, wherein fabricating the micro-electro-mechanical system structure on the first substrate further includes:

forming polysilicon over the barrier layer;

removing a portion of the polysilicon layer to define the micro-electro-mechanical system structure.

13. The method of claim 1, wherein fabricating the micro-electro-mechanical system structure on the first substrate further includes:

etching a mold within the first substrate;

forming the barrier layer over the first substrate so that a portion of the barrier layer conforms to the mold;

forming polysilicon over the barrier layer so that a portion of the polysilicon conforms to the mold; and

removing a portion of the polysilicon layer to define the micro-electro-mechanical system structure;

wherein the mold defines a tip of the micro-electro-mechanical system structure.

14. A method to fabricate a tip die to access a media in a probe storage system, the method comprising:

using a first wafer as a first substrate;

fabricating a tip on the first substrate;

depositing a first oxide layer over the tip;

using a second wafer as a second substrate;

fabricating a monolithic integrated circuit on the second substrate;

forming a second oxide layer over the monolithic integrated circuit;

arranging the first wafer and the second wafer so that the first oxide layer opposes the second oxide layer;

aligning the first wafer with the second wafer so that the tip is aligned with the monolithic integrated circuit;

contacting the first oxide layer with the second oxide layer; and

bonding the first oxide layer and the second oxide layer.

15. The method of claim 14, further comprising:

planarizing the first oxide layer after depositing the first oxide layer;

planarizing the second oxide layer after depositing the second oxide layer; and

removing the first substrate after bonding the first oxide layer and the second oxide layer.

16. The method of claim 14, wherein bonding the first oxide layer and the second oxide layer includes fusion bonding the first oxide layer and the second oxide layer.

17. The method of claim 15, further comprising:

fabricating a cantilever on the first substrate;

wherein the tip is associated with a distal end of the cantilever;

etching the first oxide layer to expose the tip and a portion of the cantilever;

depositing a sacrificial layer over the tip and portion of the cantilever;

wherein planarizing the first oxide layer includes planarizing the sacrificial layer; and

etching the sacrificial layer.

18. The method of claim 17, further comprising:

forming a via through the cantilever to a conductive interconnect of the monolithic integrated circuit; and

forming a conductive material within the via;

wherein when the conductive material is formed within the via, the tip is adapted to electrically communicate with the monolithic integrated circuit.

19. The method of claim 17, wherein the sacrificial layer is copper.

20. The method of claim 14, wherein the monolithic integrated circuit is a complementary-metal-oxide semiconductor circuit.

21. The method of claim 14, further comprising:

forming a barrier layer over the first substrate; and

wherein the barrier layer is disposed between the first substrate and the tip.

22. The method of claim 14, wherein the barrier layer comprises silicon dioxide.

23. The method of claim 14, fabricating a tip on the first substrate further includes:

etching a mold within the first substrate;

forming a barrier layer over the first substrate so that a portion of the barrier layer conforms to the mold;

forming polysilicon over the barrier layer so that a portion of the polysilicon conforms to the mold; and

wherein fabricating the cantilever on the first substrate further includes;

forming polysilicon over the barrier layer;

etching a portion of the polysilicon layer to define the cantilever.

24. A method to fabricate a tip die to access a media in a probe storage system, the method comprising:

using a first wafer as a first substrate;

etching a mold within the first substrate to define a tip;

forming a barrier layer over the first substrate so that a portion of the barrier layer conforms to the mold;

forming polysilicon over the barrier layer;

etching a portion of the polysilicon layer to define the cantilever;

depositing a first oxide layer over the cantilever;

etching the first oxide layer to expose a portion of the cantilever;

depositing a sacrificial layer over the portion of the cantilever;

planarizing the first oxide layer and the sacrificial layer;

using a second wafer as a second substrate;

fabricating a monolithic integrated circuit on the second substrate;

forming a second oxide layer over the monolithic integrated circuit;

planarizing the second oxide layer;

arranging the first wafer and the second wafer so that the first oxide layer opposes the second oxide layer;

aligning the first wafer with the second wafer so that the cantilever is aligned with the monolithic integrated circuit;

contacting the first oxide layer with the second oxide layer;

fusion bonding the first oxide layer and the second oxide layer;

etching the first substrate;

forming a via through the cantilever to a conductive interconnect of the monolithic integrated circuit;

forming a conductive material within the via;

wherein when the conductive material is formed within the via, the tip is adapted to electrically communicate with the monolithic integrated circuit;

etching the barrier layer.