METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR

• US 20080233709A1
• Filed: 03/22/2007
• Published: 09/25/2008
• Est. Priority Date: 03/22/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc., Infineon Technologies AG
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines SA (International Business Machines Corporation)
• Inventors: Stapelmann, Chris, Sievers, Michael R., Conti, Richard Anthony, Tilke, Armin T.
• Application Number:
  US11/689,884
• Publication Number:
  US 20080233709A1
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.

Claims

1. A method for removing a material from a trench in a semiconductor, comprising:

placing the semiconductor in a vacuum chamber;

admitting a reactant into the chamber at a pressure sufficient to form a film of the reactant on a surface of the material;

controlling the composition and residence time of the film on the surface of the material to etch a predetermined portion of the material; and

removing any unwanted reactant and reactant products from the chamber or surface of the material.

2. The method of claim 1, wherein the film comprises a condensed or an adsorbed layer of reactant molecules, and wherein controlling the residence time and the composition of the film comprises maintaining a temperature of the semiconductor below the temperature of a surface of the chamber to reduce condensation of the reactant on the surface of the chamber.

3. The method of claim 1, wherein the film comprises a condensed or an adsorbed layer of reactant molecules, and wherein controlling the residence time and the composition of the film comprises maintaining a temperature of the semiconductor below the temperature of any other surface in the chamber to substantially eliminate condensation of the reactant on any other surface in the chamber.

4. The method of claim 1, wherein controlling the composition and the residence time of the film comprises controlling an amount of the reactant that is admitted into the chamber.

5. The method of claim 1, wherein the semiconductor comprises at least one trench, and wherein the material comprises fill material for the at least one trench.

6. The method of claim 5, wherein the at least one trench comprises one or more shallow trench isolation structures.

7. The method of claim 5, wherein the material has a dielectric constant that is equal to or less than 3.9.

8. The method of claim 5, wherein the material is deposited by a spin-on process.

9. The method of claim 5, wherein the material is deposited by a chemical vapor deposition process.

10. The method of claim 5, wherein said material is deposited by a condensation process.

11. The method of claim 5 wherein the material is deposited by a FlowFill™

process.

12. The method of claim 1, wherein the reactant comprises NH₃ and HF.

13. The method of claim 1, wherein the reactant comprises one or more materials selected from the group consisting of HF, H₂O, NH₃, ammonium bifluoride and a combination thereof.

14. The method of claim 13, wherein each one of the one or more materials is admitted separately into the chamber under a specific temperature and pressure.

15. The method of claim 14, wherein the temperature is less than or equal to a temperature of the semiconductor, wherein the reaction chamber is pumped out, a source of the one or more materials is opened, the reaction chamber is isolated from the pump by closing a shutoff valve so that the pressure within the chamber rises rapidly to a termination pressure, and after a reaction between the film and the material is substantially complete, the source is closed and the chamber is pumped out.

16. The method of claim 1, wherein the one or more materials comprise HF and NH₃, wherein the one or more materials are used to form a condensed layer to etch at least the portion of the material, wherein a reaction between the condensed layer and the material is controlled to a self-limiting thickness by adjusting a temperature, the pressure and a gaseous composition of HF and NH₃ in the chamber.

17. The method of claim 13, wherein the one or more materials comprise HF and ammonia, and wherein the one or more materials are used to form a condensed layer having a self-terminating thickness.

18. The method of claim 1, wherein controlling the composition and residence time of the film comprises admitting the reactant into the chamber at the pressure that is greater than a condensation pressure at a temperature of the semiconductor and that is less than the condensation pressure at the temperature of a surface of the chamber.

26. An isolation structure in a semiconductor substrate formed according to the method described in claim 1.

19. A method of creating an isolation structure in a semiconductor substrate, comprising:

providing a semiconductor substrate having a trench, wherein the trench includes a bottom surface, an open top, and a side surface that extends from the bottom surface to the top;

forming a liner along the bottom surface and the side surface of the trench;

filling the trench with a dielectric material;

removing the dielectric material from a portion of the side surface of the trench adjacent the opening while leaving most of the dielectric material in the trench so as to expose the liner on the portion of the side surfaces by;

placing the semiconductor substrate in a vacuum chamber;

admitting reactant containing gas into the chamber at a sufficient pressure so as to form a film of the reactant on a surface of the dielectric material; and

controlling the composition and residence time of the film on the surface of the dielectric material so as to etch an accurate amount of the dielectric material on the substrate; and

removing any unwanted reactant and reaction products from the chamber or surface of the substrate;

depositing an oxide over the trench to a level above the opening of the trench; and

recessing the oxide down to the level of the opening of the trench.

20. The method of claim 19, wherein forming the liner comprises forming a nitride liner.

21. The method of claim 19, wherein forming the liner comprises forming an oxide liner followed by a nitride liner.

22. The method of claim 19, wherein filling the trench with a dielectric material comprises filling the filling the trench with a dielectric material that has a dielectric constant that is equal to or less than 3.9.

23. The method of claim 19, wherein depositing the oxide comprises depositing the oxide using a chemical vapor deposition process.

24. The method of claim 19, wherein recessing the oxide comprises using a chemical mechanical polishing process or a wet etch process.

25. The method of claim 19, wherein controlling the composition and the residence time of the film comprises admitting the reactant into the chamber at the pressure that is greater than a condensation pressure at a temperature of the semiconductor substrate and that is less than the condensation pressure at the temperature of a surface of the vacuum chamber.