METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
First Claim
1. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:
- providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer;
forming a second pad over said semiconductor substrate, wherein said second pad is connected to said first pad through said first opening in said passivation layer, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said passivation layer, forming a seed layer on said glue/barrier layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes said seed layer, electroplating a copper layer on said seed layer exposed by said second opening in said photoresist layer, wherein said copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometer, electroless plating a gold layer on said nickel layer in said second opening, wherein said gold layer has a thickness greater than 0.1 micrometer, after said electroless plating said gold layer, removing said photoresist layer, etching said seed layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and
wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device.
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Abstract
A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
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Citations
25 Claims
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1. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer; forming a second pad over said semiconductor substrate, wherein said second pad is connected to said first pad through said first opening in said passivation layer, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said passivation layer, forming a seed layer on said glue/barrier layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer exposes said seed layer, electroplating a copper layer on said seed layer exposed by said second opening in said photoresist layer, wherein said copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said copper layer in said second opening, wherein said nickel layer has a thickness greater than 0.5 micrometer, electroless plating a gold layer on said nickel layer in said second opening, wherein said gold layer has a thickness greater than 0.1 micrometer, after said electroless plating said gold layer, removing said photoresist layer, etching said seed layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer; forming a polymer layer on said passivation layer, wherein said forming said polymer layer comprises depositing a photosensitive polymer on said passivation layer; forming a second opening in said polymer layer, wherein said second opening exposes said first pad; forming a second pad over said polymer layer, wherein said second pad is connected to said first pad through said second opening and said first opening, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said polymer layer, forming a seed layer on said glue/barrier layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer exposes said seed layer, electroplating a copper layer on said seed layer exposed by said third opening, wherein said copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said copper layer in said third opening, wherein said nickel layer has a thickness greater than 0.5 micrometer, electroless a gold layer on said nickel layer in said third opening, wherein said gold layer has a thickness greater than 0.1 micrometer, after said electroless plating said gold layer, removing said photoresist layer, etching said seed layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for fabricating an integrated circuit die with a wirebonded wire, comprising:
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providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said second interconnect metal layer, wherein a first opening in said passivation layer exposes a first pad of said second interconnect metal layer, and wherein said passivation layer comprises an oxide layer and a nitride layer wherein said nitride layer is over said oxide layer; forming a polymer layer on said passivation layer, wherein said forming said polymer layer comprises depositing a photosensitive polymer on said passivation layer; forming a second opening in said polymer layer, wherein said second opening exposes said first pad; forming a second pad over said polymer layer, wherein said second pad is connected to said first pad through said second opening and said first opening, and wherein said forming said second pad comprises forming a glue/barrier layer over said first pad and over said polymer layer, forming a first copper layer on said glue/barrier layer, electroplating a second copper layer on said first copper layer, wherein said second copper layer has a thickness greater than 1 micrometer, electroplating a nickel layer on said second copper layer, wherein said nickel layer has a thickness greater than 0.5 micrometer, forming a gold layer on said nickel layer, wherein said gold layer has a thickness greater than 0.1 micrometer, etching said first copper layer not under said gold layer, and etching said glue/barrier layer not under said gold layer; and wirebonding said wirebonded wire to said second pad, wherein a contact area between said second pad and said wirebonded wire is directly over said active device, wherein the position of said contact area from a top view is different from that of said first pad. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification