METHOD FOR MANUFACTURING FLOATING STRUCTURE OF MICROELECTROMECHANICAL SYSTEM

• US 20080233752A1
• Filed: 10/30/2007
• Published: 09/25/2008
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: PARK, Seon-Hee, PYO, Hyeon-Bong, KO, Sang-Choon, JUN, Chi-Hoon
• Granted Patent: US 7,879,629 B2
• Time in Patent Office: Days
• US Class Current: 438/700
• CPC Class Codes: B81C 1/00801 Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer B81C1/00595, B81C1/00468 take precedence
• CPC Class Codes: B81C 2201/0133 Wet etching
• CPC Class Codes: B81C 2201/0136 by doping limited material regions

Abstract

Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

Claims

1. A method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of:

a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate;

b) forming a support layer on the sacrificial layer;

c) forming a structure to be floated on the support layer by using a subsequent process;

d) forming an etch hole exposing both side portions of the thin layer pattern; and

e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

2. The method of claim 1, further comprising the step of:

f) etching the substrate exposed through the air gap to form a cavity in the substrate after the step e).

3. The method of claim 1, wherein the step a) includes the steps of:

a1) forming a first oxide layer on the substrate;

a2) forming the thin layer pattern on the first oxide layer; and

a3) forming a second oxide layer on the substrate including the thin layer pattern.

4. The method of claim 3, wherein the step a2) includes the steps of:

a2-1) doping a part of an upper portion of the first oxide layer with impurities; and

a2-2) etching the first oxide layer such that both side portions of the doped first oxide layer correspond to the etch hole.

5. The method of claim 4, wherein the step a2-1) is performed by a doping process using POCl₃ or BBr₃.

6. The method of claim 1, wherein the impurities are phosphorus (P) or boron (B) ions.

7. The method of claim 1, wherein the thin layer pattern is formed of P₂O₅ or B₂O₃.

8. The method of claim 1, wherein the support layer is formed of nitride.

9. The method of claim 1, wherein the step e) is performed by an isotropic wet etching process.

10. The method of claim 9, wherein the isotropic wet etching process is performed by introducing a solution through the etch hole, the solution being prepared by diluting a fluoric acid (HF) solution with deionized water.

11. The method of claim 10, wherein the solution is prepared by diluting the HF solution with the deionized water at a ratio of at least approximately 1:

10.

12. The method of claim 2, wherein the step f) is performed by an anisotropic wet etching process.

13. The method of claim 1, wherein the step c) includes the steps of:

c1) forming a first conductive layer on the support layer;

c2) forming a first insulating layer to cover the conductive layer, the first insulating layer exposing the etch hole;

c3) forming a second insulating layer to cover the first insulating layer; and

c4) forming a second conductive layer on the second insulating layer, corresponding to the first conductive layer.

14. The method of claim 13, wherein the etch hole is formed by etching the second insulating layer.

15. The method of claim 13, further comprising the step of:

c5) forming a sensing layer to cover the second conductive layer after the step c4).

16. The method of claim 1, wherein the etch hole id formed in plurality.

17. The method of claim 1, wherein the structure is formed into a membrane type, a cantilever type, or a bridge type.