METHOD AND SYSTEM FOR TRANSMISSION OR RECEPTION OF FM SIGNALS UTILIZING A DDFS CLOCKED BY AN RFID PLL

• US 20080233908A1
• Filed: 05/29/2007
• Published: 09/25/2008
• Est. Priority Date: 03/19/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Rofougaran, Ahmadreza
• Granted Patent: US 7,920,893 B2
• Time in Patent Office: Days
• US Class Current: 455/185.1
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/156 One or more switches are realised in the feedback circuit of the amplifier stage
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals

Abstract

Aspects of a method and system for transmission or reception of FM signals utilizing a DDFS clocked by an RFID PLL are provided. In this regard, one or more signals utilized to transmit or receive FM communication may be generated by clocking a DDFS via a signal generated to enable RFID communication.

The DDFS may be controlled via a control word from a processor. In this regard, the control word may determine a frequency and/or phase of the signals output by the DDFS. The control word may be switched between two or more values to generate different frequencies and/or phases in different time intervals. Additionally, the control word may be adjusted to maintain a constant phase and/or frequency in spite of changes to the signal clocking the DDFS.

Claims

1. A method for signal processing, the method comprising:

generating a first signal to enable transmission and/or reception of RFID signals; and

clocking a DDFS via said generated first signal to generate one or more signals, which enables transmission or reception of frequency modulated signals.

2. The method according to claim 1, comprising generating a control word input to said DDFS that controls said generation of said one or more signals by said DDFS.

3. The method according to claim 2, comprising simulating simultaneous FM transmission and FM reception by switching said control word input to said DDFS between two values.

4. The method according to claim 2, comprising switching said control word input to said DDFS between two values in successive time intervals to perform time-division duplexing of FM transmission and FM reception.

5. The method according to claim 4, wherein said FM transmission occurs at a first frequency and said FM reception occurs at a second frequency.

6. The method according to claim 1, comprising adjusts a control word input to said DDFS, which controls said generation of said one or more signals by said DDFS, to compensate for changes in a frequency of said first signal.

7. The method according to claim 1, wherein a frequency of said first signal is within one of the following frequency bands:

868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and 5.725 to 5.875 GHz.

8. The method according to claim 1, wherein a frequency of each of said generated one or more signals is within a frequency band of 60 MHz to 130 MHz.

9. The method according to claim 1, wherein each of said generated one or more signals comprise an in-phase component and a quadrature-phase component.

10. The method according to claim 1, comprising generating said first signal via a phase locked loop.

11. The method according to claim 10, wherein said phase locked loop operates at a fixed frequency.

12. A system for signal processing, the system comprising:

one or more circuits that generate a first signal to enable transmission and/or reception of RFID signals; and

said one or more circuits clocks a DDFS via said generated first signal to generate one or more signals, which enable transmission or reception of frequency modulated signals.

13. The system according to claim 12, wherein said one or more circuits generate a control word input to said DDFS that controls said generation of said one or more signals by said DDFS.

14. The system according to claim 13, wherein said one or more circuits simulates simultaneous FM transmission and FM reception by switching said control word input to said DDFS between two values.

15. The system according to claim 13, wherein said one or more circuits switches said control word input to said DDFS between two values in successive time intervals to perform time-division duplexing of FM transmission and FM reception,

16. The system according to claim 15, wherein said FM transmission occurs at a first frequency and said FM reception occurs at a second frequency.

17. The system according to claim 12, wherein said one or more circuits adjusts a control word input to said DDFS, which controls said generation of said one or more signals by said DDFS, to compensate for changes in a frequency of said first signal

18. The system according to claim 12, wherein a frequency of said first signal is within one of the following frequency bands:

868 MHz to 928 MHz, 2.4 GHz to 2.483 GHz, and 5.725 to 5.875 GHz.

19. The system according to claim 12, wherein a frequency of each of said generated one or more signals is within a frequency band of 60 MHz to 130 MHz.

20. The system according to claim 12, wherein each of said generated one or more signals comprise an in phase component and a quadrature component.

21. The system according to claim 12, wherein said one or more circuits comprise a phase locked loop that generates said first signal.

22. The system according to claim 21, wherein said phase locked loop operates at a fixed frequency.